Design and optimization of low voltage high performance dual threshold CMOS circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Design methodology for fine-grained leakage control in MTCMOS
Proceedings of the 2003 international symposium on Low power electronics and design
Leakage aware dynamic voltage scaling for real-time embedded systems
Proceedings of the 41st annual Design Automation Conference
Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment
Proceedings of the 41st annual Design Automation Conference
A combined gate replacement and input vector control approach for leakage current reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Models and algorithms for bounds on leakage in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Algorithms for minimizing standby power in deep submicrometer, dual-Vt CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Static leakage reduction through simultaneous Vt/Tox and state assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Leakage power and circuit aging cooptimization by gate replacement techniques
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing NBTI-induced processor wearout by exploiting the timing slack of instructions
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
| Hi-index | 0.00 |
Dual Vt assignment and input vector control are two tightly coupled leakage reduction techniques. We study how to apply them effectively to a circuit to minimize the static leakage power. We argue that simply combining them in a serial fashion will not reach their full potential in leakage reduction. To show this, we propose a heuristic algorithm that integrates them into a single optimization loop by assigning the value for primary inputs and Vt for logic gates simultaneously. Our algorithm leverages the fact that both input vector and threshold voltage Vt have great impact on a gate's leakage at standby mode and avoids to assign a gate both low Vt and input vector that results high leakage. The selection of input vector and the assignment of Vt are integrated seamlessly through the concepts of leakage observability, worst leakage state, and path factor. The proposed algorithm has a low run time complexity and achieves an average 15% leakage reduction on all the ISCAS and MCNC benchmarks over the serial combination of input vector selection and dual Vt assignment.