Design and optimization of low voltage high performance dual threshold CMOS circuits

Authors:
Liqiong Wei;Zhanping Chen;Mark Johnson;Kaushik Roy;Vivek De
Affiliations:
School of Electrical and Computer Engineering, Purdue University, W. Lafayette, IN;School of Electrical and Computer Engineering, Purdue University, W. Lafayette, IN;School of Electrical and Computer Engineering, Purdue University, W. Lafayette, IN;School of Electrical and Computer Engineering, Purdue University, W. Lafayette, IN;Microcomputer Research Labs., Intel Corp., Hillsboro, OR
Venue:
DAC '98 Proceedings of the 35th annual Design Automation Conference
Year:
1998

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Abstract

Reduction in leakage power has become an important concern in low voltage, low power and high performance applications. In this paper, we use dual threshold technique to reduce leakage power by assigning high threshold voltage to some transistors in non-critical paths, and using low-threshold transistors in critical paths. In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high threshold voltage. A general standby leakage current model which has been verified by IISPICE is used to estimate standby leakage power. Results show that dual threshold technique is good for power reduction during both standby and active modes. The standby leakage power savings for some ISCAS benchmarks can be more than 50%.