Design and optimization of low voltage high performance dual threshold CMOS circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2002 international symposium on Low power electronics and design
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Comparative analysis of conventional and statistical design techniques
Proceedings of the 44th annual Design Automation Conference
Stress aware layout optimization
Proceedings of the 2008 international symposium on Physical design
Leakage power reduction using stress-enhanced layouts
Proceedings of the 45th annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improving dual Vt technology by simultaneous gate sizing and mechanical stress optimization
Proceedings of the International Conference on Computer-Aided Design
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Process-induced mechanical stress is used to enhance carrier transport and achieve higher drive currents in current complementary metal-oxide-semiconductor technologies. This paper explores how to fully exploit the layout dependence of stress enhancement and proposes a circuit-level, block-based, stress-enhanced optimization algorithm that uses stress-optimized layouts in conjunction with dual-Vth assignment to achieve optimal power-performance tradeoffs. We begin by studying how channel stress and drive current depend on layout parameters such as active area length and contact placement, while considering all layout-dependent sources of mechanical stress in a 65 nm industrial process. We then investigate the three main layout properties that impact mechanical stress in this process and discuss how to improve stress-based performance enhancement in standard cell libraries. While varying the stress-altering layout properties of a number of standard cells in a 65 nm industrial library, we show that "dual-stress" standard cell layouts (analogous to "dual-Vth") can be designed to achieve drive current differences up to ∼14% while incurring less than half the leakage penalty of dual-Vth. Therefore, when the flexibility of "dualstress" assignment is combined with dual-Vth assignment (within the proposed joint optimization framework), simulation results for a set of benchmark circuits show that leakage is reduced by ∼24% on average, for iso-delay, when compared to dual-Vth assignment. Since mobility enhancement does not incur the exponential leakage penalty associated with Vth assignment, our optimization technique is ideal for leakage power reduction. However, our framework can also be used to achieve higher performance circuits for iso-leakage and our joint optimization framework can be used to reduce delay on average by ∼5%. In both cases, the proposed method only incurs a small area penalty (