Comparative analysis of conventional and statistical design techniques

Authors:
Steven M. Burns;Mahesh Ketkar;Noel Menezes;Keith A. Bowman;James W. Tschanz;Vivek De
Affiliations:
Intel Corporation, Hillsboro, OR;Intel Corporation, Hillsboro, OR;Intel Corporation, Hillsboro, OR;Intel Corporation, Hillsbor, OR;Intel Corporation, Hillsbor, OR;Intel Corporation, Hillsbor, OR
Venue:
Proceedings of the 44th annual Design Automation Conference
Year:
2007

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Abstract

We explore the power benefits of changing a microprocessor path histogram through circuit sizing based on statistical timing analysis and optimization (STAO) versus a deterministic timing approach that uses statistical design to establish a global guardband followed by conventional optimization (SDGG). Using an analytical modeling approach, we quantify the differences in total power between the two approaches while maintaining an equivalent performance distribution. For a relative 1σ random WID stage delay variation of 5% and representative microprocessor critical paths, the analysis indicates that the STAO approach enables ~2% power reduction over the SDGG approach. To achieve a 4% and 6% power reduction through the STAO approach, the process variation needs to increase by a factor of 2x and 4x, respectively.