Design and optimization of low voltage high performance dual threshold CMOS circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Proceedings of the 2002 international symposium on Low power electronics and design
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Comparative analysis of conventional and statistical design techniques
Proceedings of the 44th annual Design Automation Conference
Exploiting STI stress for performance
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Stress aware layout optimization
Proceedings of the 2008 international symposium on Physical design
STEEL: a technique for stress-enhanced standard cell library design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Modeling of layout-dependent stress effect in CMOS design
Proceedings of the 2009 International Conference on Computer-Aided Design
Layout-dependent STI stress analysis and stress-aware RF/analog circuit design optimization
Proceedings of the 2009 International Conference on Computer-Aided Design
A framework for early and systematic evaluation of design rules
Proceedings of the 2009 International Conference on Computer-Aided Design
Mechanical stress aware optimization for leakage power reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Stress aware layout optimization leveraging active area dependent mobility enhancement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Stress aware switching activity driven low power design of critical paths in nanoscale CMOS circuits
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
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In recent years, process-induced mechanical stress has emerged as a useful manufacturing technique that enhances carrier transport and increases drive currents. This improvement in current has helped to compensate the decline of device scaling factors in parameters such as tox, Vth, and Vdd. In this work, we propose stress as a means to achieve optimal power-performance trade-off by combining stress-based, performance-enhanced standard cell assignment with dual-Vth assignment. We study how stress-induced performance enhancements are affected by layout properties and improve standard cell layouts so that performance gains are maximized. We then develop a circuit-level, block-based, stress-enhanced optimization algorithm that includes all layout-dependent sources of mechanical stress. By combining the two performance enhancement techniques (stress-based and dual-Vth) for a set of benchmark circuits, we find that our stress-aware optimization, decreases leakage by ~24% on average, for iso-delay, when compared to dual-Vth assignment. Similarly, for iso-leakage, our optimization algorithm reduces delay on average by 5%. In both cases, the proposed method only incurs a small area penalty (