Stress-Aware Design Methodology
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Leakage power reduction using stress-enhanced layouts
Proceedings of the 45th annual Design Automation Conference
STEEL: a technique for stress-enhanced standard cell library design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
STI stress aware placement optimization based on geometric programming
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Modeling of layout-dependent stress effect in CMOS design
Proceedings of the 2009 International Conference on Computer-Aided Design
Layout-dependent STI stress analysis and stress-aware RF/analog circuit design optimization
Proceedings of the 2009 International Conference on Computer-Aided Design
3-2-1 contact: an experimental approach to the analysisof contacts in 45 nm and below
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Stress aware layout optimization leveraging active area dependent mobility enhancement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
D-A converter based variation analysis for analog layout design
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Layout-aware variation evaluation of analog circuits and its validity on op-amp designs
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Stress-driven 3D-IC placement with TSV keep-out zone and regularity study
Proceedings of the International Conference on Computer-Aided Design
Structured analog circuit design and MOS transistor decomposition for high accuracy applications
Proceedings of the International Conference on Computer-Aided Design
Decoupling capacitor design strategy for minimizing supply noise of ultra low voltage circuits
Proceedings of the 49th Annual Design Automation Conference
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Starting at the 65nm node, stress engineering to improve performance of transistors has been a major industry focus. An intrinsic stress source - shallow trench isolation - has not been fully utilized up to now for circuit performance improvement. In this paper, we present a new methodology that combines detailed placement and active-layer fill insertion to exploit STI stress for performance improvement. We perform process simulation of a production 65nm STI technology to generate mobility and delay impact models for STI stress. Based on these models, we are able to perform STI stress-aware delay analysis of critical paths using SPICE. We then present our timing-driven optimization of STI stress in standard cell designs, using detailed placement perturbation to optimize PMOS performance and active-layer fill insertion to optimize NMOS performance. We assess our optimization on small designs implemented with a 65nm production cell library and a standard synthesis, place and route flow. Our timing-driven optimization of STI stress impacts can improve clock frequency by between 7% to 11%. The frequency improvement through exploitation of STI stress comes at practically zero cost in terms of design area and wirelength.