Exploiting STI stress for performance
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
A study of Through-Silicon-Via impact on the 3D stacked IC layout
Proceedings of the 2009 International Conference on Computer-Aided Design
TSV stress aware timing analysis with applications to 3D-IC layout optimization
Proceedings of the 47th Design Automation Conference
Kraftwerk2—A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Chemical-mechanical polishing aware application-specific 3D NoC design
Proceedings of the International Conference on Computer-Aided Design
Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs
Proceedings of the 49th Annual Design Automation Conference
TSV array utilization in low-power 3D clock network design
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Thermomechanical stress-aware management for 3D IC designs
Proceedings of the Conference on Design, Automation and Test in Europe
Crosstalk avoidance codes for 3D VLSI
Proceedings of the Conference on Design, Automation and Test in Europe
An accurate semi-analytical framework for full-chip TSV-induced stress modeling
Proceedings of the 50th Annual Design Automation Conference
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC
Communications of the ACM
On accurate full-chip extraction and optimization of TSV-to-TSV coupling elements in 3D ICs
Proceedings of the International Conference on Computer-Aided Design
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Through-silicon via (TSV) fabrication causes tensile stress around TSVs which results in significant carrier mobility variation in the devices in their neighborhood. Keep-out zone (KOZ) is a conservative way to prevent any devices/cells from being impacted by the TSV-induced stress. However, owing to already large TSV size, large KOZ can significantly reduce the placement area available for cells, thus requiring larger dies which negate improvement in wirelength and timing due to 3D integration. In this paper, we study the impact of KOZ dimension on stress, carrier mobility variation, area, wirelength, and performance of 3D ICs. We demonstrate that, instead of requiring large KOZ, 3D-IC placers must exploit TSV stress-induced carrier mobility variation to improve the timing and area objectives during placement. We propose a new TSV stress-driven force-directed 3D placement that consistently provides placement result with, on average, 21.6% better worst negative slack (WNS) and 28.0% better total negative slack (TNS) than wirelength-driven placement.