The road to 3D EDA tool readiness
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Pre-bond testable low-power clock tree design for 3D stacked ICs
Proceedings of the 2009 International Conference on Computer-Aided Design
Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs
Proceedings of the 2009 International Conference on Computer-Aided Design
A study of Through-Silicon-Via impact on the 3D stacked IC layout
Proceedings of the 2009 International Conference on Computer-Aided Design
Robust clock tree synthesis with timing yield optimization for 3D-ICs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Assembling 2D blocks into 3D chips
Proceedings of the 2011 international symposium on Physical design
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC
Proceedings of the 48th Design Automation Conference
Proceedings of the International Conference on Computer-Aided Design
Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC
Proceedings of the International Conference on Computer-Aided Design
Stress-driven 3D-IC placement with TSV keep-out zone and regularity study
Proceedings of the International Conference on Computer-Aided Design
TSV array utilization in low-power 3D clock network design
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Circuit reliability: from physics to architectures
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
Thermal stress aware 3D-IC statistical static timing analysis
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
An accurate semi-analytical framework for full-chip TSV-induced stress modeling
Proceedings of the 50th Annual Design Automation Conference
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC
Communications of the ACM
Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs
Integration, the VLSI Journal
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As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and silicon have different coefficients of thermal expansion (CTE), TSV causes silicon deformation due to different temperatures at chip manufacturing and operating. The widely used TSV fill material is copper which causes tensile stress on silicon near TSV. In this paper, we propose systematic TSV stress aware timing analysis and show how to optimize layout for better performance. First, we generate a stress contour map with an analytical radial stress model. Then, the tensile stress is converted to hole and electron mobility variations depending on geometric relation between TSVs and transistors. Mobility variation aware cell library and netlist are generated and incorporated in an industrial timing engine for 3D-IC timing analysis. It is interesting to observe that rise and fall time react differently to stress and relative locations with respect to TSVs. Overall, TSV stress induced timing variations can be as much as ± 10% for an individual cell. Thus as an application for layout optimization, we can exploit the stress-induced mobility enhancement to improve timing on critical cells. We show that stress-aware perturbation could reduce cell delay by up to 14.0% and critical path delay by 6.5% in our test case.