TSV stress aware timing analysis with applications to 3D-IC layout optimization
Proceedings of the 47th Design Automation Conference
Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC
Proceedings of the 48th Design Automation Conference
Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC
Proceedings of the International Conference on Computer-Aided Design
Stress-driven 3D-IC placement with TSV keep-out zone and regularity study
Proceedings of the International Conference on Computer-Aided Design
Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs
Proceedings of the 49th Annual Design Automation Conference
Proceedings of the International Conference on Computer-Aided Design
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TSV-induced stress is an important issue in 3D IC design since it leads to serious reliability problems and influences device performance. Existing finite element method can provide accurate analysis for the stress of simple TSV placement, but is not scalable to larger designs due to its expensive memory consumption and high run time. On the contrary, linear superposition method is efficient to analyze stress in full-chip scale, but sometimes it fails to provide an accurate estimation since it neglects the stress induced by interactions between TSVs. In this paper we propose an accurate two-stage semi-analytical framework for full-chip TSV-induced stress modeling. In addition to the linear superposition, we characterize the stress induced by interactions between TSVs to provide more accurate full-chip modeling. Experimental results demonstrate that the proposed framework can significantly improve the accuracy of linear superposition method with reasonable overhead in run time.