Finite Element Analysis: Theory and Application with Ansys
Finite Element Analysis: Theory and Application with Ansys
Thermal via placement in 3D ICs
Proceedings of the 2005 international symposium on Physical design
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Temperature-aware routing in 3D ICs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Interconnect and Thermal-aware Floorplanning for 3D Microprocessors
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Bus-aware microarchitectural floorplanning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
3D-Stacked Memory Architectures for Multi-core Processors
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Thermal optimization in multi-granularity multi-core floorplanning
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures
Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures
Hotspot: acompact thermal modeling methodology for early-stage VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Thermomechanical stress-aware management for 3D IC designs
Proceedings of the Conference on Design, Automation and Test in Europe
An accurate semi-analytical framework for full-chip TSV-induced stress modeling
Proceedings of the 50th Annual Design Automation Conference
Compact lateral thermal resistance modeling and characterization for TSV and TSV array
Proceedings of the International Conference on Computer-Aided Design
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The three-dimensional integrated circuits (3D ICs) offer performance advantages thanks to the increased bandwidth and reduced wire-length enabled by through-silicon-via structures (TSVs). Traditionally TSVs have been considered to improve the thermal conductivity in the vertical direction. However, the lateral thermal blockage effect becomes increasingly important for TSV via farms (a cluster of TSV vias used for signal bus connections between layers). TSV farms can cause different thermal effects on different layers due to the unequal x,y,z thermal conductivities. This can exhibit itself as thermal improvement in the vertical heat flow, at the same time lateral heat blockage effects in thinned pass-through layers. In this paper, we propose a thermalaware via farm placement technique for 3D ICs to minimize lateral heat blockages caused by dense signal bus TSV structures. By incorporating thermal conductivity profile of via farm blocks in the design flow and enabling placement/aspect ratio optimization, the corresponding hotspots can be minimized within the wire-length and area constraints.