Strategies for improving the parametric yield and profits of 3D ICs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Bus-aware microarchitectural floorplanning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A modular 3d processor for flexible product design and technology migration
Proceedings of the 5th conference on Computing frontiers
Proceedings of the 2009 SPEC Benchmark Workshop on Computer Performance Evaluation and Benchmarking
Thermal optimization in multi-granularity multi-core floorplanning
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A criticality-driven microarchitectural three dimensional (3D) floorplanner
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Quantifying and coping with parametric variations in 3D-stacked microarchitectures
Proceedings of the 47th Design Automation Conference
Energy-efficient variable-flow liquid cooling in 3D stacked architectures
Proceedings of the Conference on Design, Automation and Test in Europe
Dynamic thermal management in 3D multicore architectures
Proceedings of the Conference on Design, Automation and Test in Europe
Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling
Microelectronics Journal
Proceedings of the 13th annual conference on Genetic and evolutionary computation
Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Token3D: reducing temperature in 3d die-stacked CMPs through cycle-level power control mechanisms
Euro-Par'11 Proceedings of the 17th international conference on Parallel processing - Volume Part I
Power profiling-guided floorplanner for thermal optimization in 3D multiprocessor architectures
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Fuzzy control for enforcing energy efficiency in high-performance 3D systems
Proceedings of the International Conference on Computer-Aided Design
Recent thermal management techniques for microprocessors
ACM Computing Surveys (CSUR)
Reliability-aware platform optimization for 3D chip multi-processors
The Journal of Supercomputing
Proceedings of the 49th Annual Design Automation Conference
Full Length Article: 3D thermal-aware floorplanner using a MILP approximation
Microprocessors & Microsystems
3D thermal-aware floorplanner using a MOEA approximation
Integration, the VLSI Journal
Proceedings of the 2013 ACM international symposium on International symposium on physical design
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This paper presents the first multiobjective microarchitectural floorplanning algorithm for high-performance processors implemented in two-dimensional (2-D) and three-dimensional (3-D) ICs. The floorplanner takes a microarchitectural netlist and determines the dimension as well as the placement of the functional modules into single- or multiple-device layers while simultaneously achieving high performance and thermal reliability. The traditional design objectives such as area and wirelength are also considered. The 3-D floorplanning algorithm considers the following 3-D-specific issues: vertical overlap optimization and bonding-aware layer partitioning. The hybrid floorplanning approach combines linear programming and simulated annealing, which is shown to be very effective in obtaining high-quality solutions in a short runtime under multiobjective goals. This paper provides comprehensive experimental results on making tradeoffs among performance, thermal, area, and wirelength for both 2-D and 3-D ICs