Partition-driven standard cell thermal placement
Proceedings of the 2003 international symposium on Physical design
The Impact of Technology Scaling on Lifetime Reliability
DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
Thermal-Aware Floorplanning Using Genetic Algorithms
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Wire congestion and thermal aware 3D global placement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
3D floorplanning with thermal vias
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A novel thermal optimization flow using incremental floorplanning for 3D ICs
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Performance and thermal-aware Steiner routing for 3-D stacked ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Adaptive Task Migration Policies for Thermal Control in MPSoCs
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
A fast and elitist multiobjective genetic algorithm: NSGA-II
IEEE Transactions on Evolutionary Computation
A Memetic Algorithm for VLSI Floorplanning
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
A matrix synthesis approach to thermal placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cell-level placement for improving substrate thermal distribution
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
Heat removal and power density distribution delivery have become two major reliability concerns in 3D stacked technology. Additionally, the placement of Through-Silicon-Vias (TSVs) for connecting different layers is one of the key issues in 3D technology. Although a few recent works have considered thermal-aware placement of cores in chip multi-processor architectures, the concepts of 3D and TSVs have not been conveniently incorporated. Therefore, new suitable exploration methods for the 3D thermal-aware floorplaning problem need to be developed. In this paper we analyze the benefits of two different exploration techniques for the floorplanning problem: Multi-Objective Genetic Algorithm (MOGA) and a Mixed Integer Linear Program (MILP). We present a novel algorithm that uses MILP to minimize average temperature in the 3D chip, whereas uses MOGA to insert TSVs, connecting the layers while the total wire length is minimized. Our experiments with two different 3D chips show that our algorithm achieves 10% reduction in the maximum temperature and thermal gradient.