Proceedings of the 13th annual conference on Genetic and evolutionary computation
A run-time task migration scheme for an adjustable issue-slots multi-core processor
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
3D thermal-aware floorplanner using a MOEA approximation
Integration, the VLSI Journal
On the design space exploration through the Hellfire Framework
Journal of Systems Architecture: the EUROMICRO Journal
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In deep submicron circuits, high temperatures have created critical issues in reliability, timing, performance, coolings costs and leakage power. Task migration techniques have been proposed to manage efficiently the thermal distribution in multi-processor systems but at the cost of important performance penalties. While traditional techniques have focused on reducing the average temperature of the chip, they have not considered the effect that temperature gradients have in system reliability. In this work, we explore the benefits of thermal-aware task migration techniques for embedded multi-processor systems. We propose several policies that are able to reduce the average temperature of the chip and the thermal gradients with a negligible performance overhead. With our techniques, hot spots and temperature gradients are decreased up to 30% with respect to state-of-the-art thermal management approaches.