Proceedings of the 6th international workshop on Hardware/software codesign
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design
Proceedings of the conference on Design, automation and test in Europe
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A Generic RTOS Model for Real-time Systems Simulation with SystemC
Proceedings of the conference on Design, automation and test in Europe - Volume 3
RTOS Modeling for System Level Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A contextual resources use: a proof of concept through the APACHES' platform
DDECS '06 Proceedings of the 2006 IEEE Design and Diagnostics of Electronic Circuits and systems
Introducing preemptive scheduling in abstract RTOS models using result oriented modeling
Proceedings of the conference on Design, automation and test in Europe
RSP '08 Proceedings of the 2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Novel task migration framework on configurable heterogeneous MPSoC platforms
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A decentralised task mapping approach for homogeneous multiprocessor network-on-chips
International Journal of Reconfigurable Computing - Selected papers from ReCoSoc08
Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms
Journal of Systems Architecture: the EUROMICRO Journal
Adaptive Task Migration Policies for Thermal Control in MPSoCs
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
Run-time spatial resource management for real-time applications on heterogeneous MPSoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Dynamic and adaptive allocation of applications on MPSoC platforms
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Dynamic Task Mapping for MPSoCs
IEEE Design & Test
Multi-task dynamic mapping onto NoC-based MPSoCs
Proceedings of the 24th symposium on Integrated circuits and systems design
Task model suitable for dynamic load balancing of real-time applications in NoC-based MPSoCs
ICCD '12 Proceedings of the 2012 IEEE 30th International Conference on Computer Design (ICCD 2012)
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Embedded systems have faced dramatic and extensive changes throughout the past years leading to each more complex designs. Thus, this article presents the Hellfire Framework, which implements a design space exploration tool based on two basic steps: explore and refine. The tool leads the designer through three main different levels of abstraction: (i) application level; (ii) OS level, and; (iii) hardware architecture level. In the application level, the initial input is a task graph that represents the application's behavior. The resulting application (divided in tasks) uses the OS we provide (and its system calls) to perform varied operations. The OS itself can be mainly configured in terms of real-time scheduling and memory occupation. Finally, the hardware architecture level allows to choose parameters regarding the processor frequency and communication infrastructure. The framework guides the designer through these levels in an explore and refine fashion so that, from a high level description of the application, the entire platform can be assembled with proper design exploration. Results show the exploration and refinement steps in the three levels we propose in different applications for MPSoC-based systems.