Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
A universal technique for fast and flexible instruction-set architecture simulation
Proceedings of the 39th annual Design Automation Conference
Scheduling Algorithms
The MIMOLA design system a computer aided digital processor design method
DAC '79 Proceedings of the 16th Design Automation Conference
Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance
Proceedings of the 31st annual international symposium on Computer architecture
Scheduling for heterogeneous processors in server systems
Proceedings of the 2nd conference on Computing frontiers
The Impact of Performance Asymmetry in Emerging Multicore Architectures
Proceedings of the 32nd annual international symposium on Computer Architecture
Dynamic thread assignment on heterogeneous multiprocessor architectures
Proceedings of the 3rd conference on Computing frontiers
Overview of the MPSoC design challenge
Proceedings of the 43rd annual Design Automation Conference
SHAPES:: a tiled scalable software hardware architecture platform for embedded systems
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Soft Real-Time Scheduling on Performance Asymmetric Multicore Platforms
RTAS '07 Proceedings of the 13th IEEE Real Time and Embedded Technology and Applications Symposium
ARCS'11 Proceedings of the 24th international conference on Architecture of computing systems
Current Techniques and Future Trends in ES's Virtualization
Software—Practice & Experience
Enabling Adaptive Techniques in Heterogeneous MPSoCs Based on Virtualization
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
On the advantage of time-varying diversity of workload on functionally asymmetric multi-core
Proceedings of International Workshop on Adaptive Self-tuning Computing Systems
On the design space exploration through the Hellfire Framework
Journal of Systems Architecture: the EUROMICRO Journal
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Heterogeneous MPSoC architectures can provide higher performance and flexibility with less power consumption and lower cost than homogeneous ones. However, as processor instruction sets of general heterogeneous MPSoCs are not identical, tasks migration between two heterogeneous processors is not possible. To enable this function, we propose to build one specific heterogeneous MPSoC platform in which all heterogeneous processors are based on the same core instruction set for the operating system realization. Different extended instructions can be added for different processors to improve the system performance. Tasks can be migrated from one processor to another only if the target processor has all instructions which can meet the execution requirement of this task. This paper concentrates on the infrastructure that is necessary to support the scheduling and migration of tasks between the processors. By using the Motion-JPEG case study, we confirm that our task migration framework can achieve higher processor usage rate and more flexibility.