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Best of Both Latency and Throughput
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Proceedings of the 33rd annual international symposium on Computer Architecture
Multiple Instruction Stream Processor
Proceedings of the 33rd annual international symposium on Computer Architecture
Core architecture optimization for heterogeneous chip multiprocessors
Proceedings of the 15th international conference on Parallel architectures and compilation techniques
Computation spreading: employing hardware migration to specialize CMP cores on-the-fly
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Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
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Proceedings of the 34th annual international symposium on Computer architecture
Impact of process variations on multicore performance symmetry
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Proceedings of the 21st annual international conference on Supercomputing
Fairness enforcement in switch on event multithreading
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Architectural contesting: exposing and exploiting temperamental behavior
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Proceedings of the 2007 ACM/IEEE conference on Supercomputing
Dma-based prefetching for i/o-intensive workloads on the cell architecture
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Predictive thread-to-core assignment on a heterogeneous multi-core processor
Proceedings of the 4th workshop on Programming languages and operating systems
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ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
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Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Multitasking workload scheduling on flexible-core chip multiprocessors
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Meeting points: using thread criticality to adapt multicore hardware to parallel regions
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
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HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Novel task migration framework on configurable heterogeneous MPSoC platforms
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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IWMSE '09 Proceedings of the 2009 ICSE Workshop on Multicore Software Engineering
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Proceedings of the 19th international conference on Parallel architectures and compilation techniques
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ACM Transactions on Computer Systems (TOCS)
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ACM Transactions on Architecture and Code Optimization (TACO)
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Performance asymmetry in multicore architectures arises when individual cores have different performance. Building such multicore processors is desirable because many simple cores together provide high parallel performance while a few complex cores ensure high serial performance. However, application developers typically assume computational cores provide equal performance, and performance asymmetry breaks this assumption. This paper is concerned with the behavior of commercial applications running on performance asymmetric systems. We present the first study investigating the impact of performance asymmetry on a wide range of commercial applications using a hardware prototype. We quantify the impact of asymmetry on an applicationýs performance variance when run multiple times, and the impact on the applicationýs scalability. Performance asymmetry adversely affects behavior of many workloads. We study ways to eliminate these effects. In addition to asymmetry-aware operating system kernels, the application often itself needs to be aware of performance asymmetry for stable and scalable performance.