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Selective cache ways: on-demand cache resource allocation
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Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures
IEEE Computer Architecture Letters
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ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon
IEEE Design & Test
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ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
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Mining tree-structured data on multicore systems
Proceedings of the VLDB Endowment
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IEEE Transactions on Circuits and Systems for Video Technology
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AASH: an asymmetry-aware scheduler for hypervisors
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Memory-, bandwidth-, and power-aware multi-core for a graph database workload
ARCS'11 Proceedings of the 24th international conference on Architecture of computing systems
Run-time energy management of manycore systems through reconfigurable interconnects
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Efficient and scalable scheduling for performance heterogeneous multicore systems
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Execution migration in a heterogeneous-ISA chip multiprocessor
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Energy consumption in mobile devices: why future systems need requirements–aware energy scale-down
PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
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Lucky scheduling for energy-efficient heterogeneous multi-core systems
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This paper proposes and evaluates single-ISA heterogeneousmulti-core architectures as a mechanism to reduceprocessor power dissipation. Our design incorporatesheterogeneous cores representing different points inthe power/performance design space; during an application'sexecution, system software dynamically chooses themost appropriate core to meet specific performance andpower requirements.Our evaluation of this architecture shows significant energybenefits. For an objective function that optimizes forenergy efficiency with a tight performance threshold, for 14SPEC benchmarks, our results indicate a 39% average energyreduction while only sacrificing 3% in performance.An objective function that optimizes for energy-delay withlooser performance bounds achieves, on average, nearly afactor of three improvement in energy-delay product whilesacrificing only 22% in performance. Energy savings aresubstantially more than chip-wide voltage/frequency scaling.