Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
An ultra low-power processor for sensor networks
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Energy Optimization of Subthreshold-Voltage Sensor Network Processors
Proceedings of the 32nd annual international symposium on Computer Architecture
Multi-processor computer system having low power consumption
PACS'02 Proceedings of the 2nd international conference on Power-aware computer systems
Design and implementation of an all-CMOS 802.11a wireless LAN chipset
IEEE Communications Magazine
Exploring parallelization for medium access schemes on many-core software defined radio architecture
Proceedings of the second workshop on Software radio implementation forum
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Considerable work has been devoted to studying flexible computation structures for the physical layer of a software defined radio (SDR) terminal. However there has been almost no research on protocol processors for the upper layer protocols such as the media access control (MAC) and link protocol. A general purpose processor (GPP) is sufficient for the protocol processing of a single mode terminal. However, in the case of a multi-mode system required for SDR, there is a very wide set of possibilities for the MAC layer. In principle these too could be handled by a GPP. However, we show that a better solution is to use a GPP augmented by a small supplemental processor. The GPP is responsible for the relatively complex protocol operations in the active mode, and the supplemental processor handles the idle mode operations. This separation of responsibilities simplifies the implementation of hard real-time responses required by some protocols (for example IEEE 802.11), while maintaining the programmability needed to handle a wide range of protocols. In addition, this organization allows a significant power savings in the idle mode. This is important because the protocol processor must process a large number of tiny idle mode tasks whose aggregate effect over time dominates the power consumption in a wireless termina.As part of our study we develop a hardware model of the supplemental processor in Verilog and its software model in C. Using commercial CAD tools we synthesized out design and evaluated the power consumption and response time of the platform. Our results show that the proposed platform meets the real-time deadlines at low power while maintaining programmability.