Automatic translation of FORTRAN programs to vector form
ACM Transactions on Programming Languages and Systems (TOPLAS)
Power analysis of a 32-bit embedded microcontroller
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
The design and use of simplepower: a cycle-accurate energy estimation tool
Proceedings of the 37th Annual Design Automation Conference
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Design issues for dynamic voltage scaling
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Voltage scheduling in the IpARM microprocessor system
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
A framework for dynamic energy efficiency and temperature management
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Power aware microarchitecture resource scaling
Proceedings of the conference on Design, automation and test in Europe
Reducing leakage in a high-performance deep-submicron instruction cache
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Fast, flexible, cycle-accurate energy estimation
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Compiler-directed dynamic voltage/frequency scheduling for energy reduction in microprocessors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Dependence graphs and compiler optimizations
POPL '81 Proceedings of the 8th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Thermal Management System for High Performance PowerPCTM Microprocessors
COMPCON '97 Proceedings of the 42nd IEEE International Computer Conference
A scheduling model for reduced CPU energy
FOCS '95 Proceedings of the 36th Annual Symposium on Foundations of Computer Science
Dynamic Thermal Management for High-Performance Microprocessors
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Conserving disk energy in network servers
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Turducken: hierarchical power management for mobile devices
Proceedings of the 3rd international conference on Mobile systems, applications, and services
A dual-processor solution for the MAC layer of a software defined radio terminal
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Comparison of scheduling schemes for on-demand IaaS requests
Journal of Systems and Software
| Hi-index | 0.00 |
Energy consumption of any component in a system may sometimes constitute just a small percentage of that of the overall system, making it necessary to address the issue of energy efficiency across the entire range of system components, from memory, to the CPU, to peripherals. Presented is a hardware architecture for detecting regions of application execution at runtime, for which there is opportunity to run a device at a slightly lower performance level, by reducing the operating frequency and voltage, to save energy. The proposed architecture, the Power Adaptation Unit (PAU) may be used to control the operating voltage of various system components, ranging from the CPU core, to memory and peripherals. An evaluation of the tradeoffs in performance versus energy savings and hardware cost of the PAU is conducted, along with results on its efficacy for a set of benchmarks. It is shown that on the average, a single entry PAU provides energy savings of 27%, with a corresponding performance degradation of 0.75% for the SPEC CPU 2000 integer and floating point benchmarks investigated.