Wattch: a framework for architectural-level power analysis and optimizations

Authors:
David Brooks;Vivek Tiwari;Margaret Martonosi
Affiliations:
Department of Electrical Engineering, Princeton University;Intel Corporation;Department of Electrical Engineering, Princeton University
Venue:
Proceedings of the 27th annual international symposium on Computer architecture
Year:
2000

Citing 23
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ACM Transactions on Architecture and Code Optimization (TACO)
Quality-of-service and error control techniques for mesh-based network-on-chip architectures

Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach

Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Transition aware scheduling: increasing continuous idle-periods in resource units

Proceedings of the 2nd conference on Computing frontiers
An efficient wakeup design for energy reduction in high-performance superscalar processors

Proceedings of the 2nd conference on Computing frontiers
Drowsy region-based caches: minimizing both dynamic and static power dissipation

Proceedings of the 2nd conference on Computing frontiers
Execution cache-based microarchitecture power-efficient superscalar processors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variability and energy awareness: a microarchitecture-level perspective

Proceedings of the 42nd annual Design Automation Conference
Low power network processor design using clock gating

Proceedings of the 42nd annual Design Automation Conference
Dynamic functional unit assignment for low power

The Journal of Supercomputing
RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence

Proceedings of the 32nd annual international symposium on Computer Architecture
Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines

Proceedings of the 32nd annual international symposium on Computer Architecture
Energy-Effectiveness of Pre-Execution and Energy-Aware P-Thread Selection

Proceedings of the 32nd annual international symposium on Computer Architecture
Exploiting Structural Duplication for Lifetime Reliability Enhancement

Proceedings of the 32nd annual international symposium on Computer Architecture
Fuzzy Memoization for Floating-Point Multimedia Applications

IEEE Transactions on Computers
Energy-efficient and high-performance instruction fetch using a block-aware ISA

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Energy-aware fetch mechanism: trace cache and BTB customization

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Understanding the energy efficiency of SMT and CMP with multiclustering

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Region-level approximate computation reuse for power reduction in multimedia applications

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Joint exploration of architectural and physical design spaces with thermal consideration

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Coordinated, distributed, formal energy management of chip multiprocessors

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Runtime identification of microprocessor energy saving opportunities

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Bounds on power savings using runtime dynamic voltage scaling: an exact algorithm and a linear-time heuristic approximation

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Power-aware code scheduling for clusters of active disks

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Synonymous address compaction for energy reduction in data TLB

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Lifetime Reliability: Toward an Architectural Solution

IEEE Micro
Efficient behavior-driven runtime dynamic voltage scaling policies

CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A sink-n-hoist framework for leakage power reduction

Proceedings of the 5th ACM international conference on Embedded software
Reducing data cache leakage energy using a compiler-based approach

ACM Transactions on Embedded Computing Systems (TECS)
Combined circuit and architectural level variable supply-voltage scaling for low power

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Toward a multiple clock/voltage island design style for power-aware processors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power, low-complexity instruction issue using compiler assistance

Proceedings of the 19th annual international conference on Supercomputing
Thread-Level Speculation on a CMP can be energy efficient

Proceedings of the 19th annual international conference on Supercomputing
Compiler Directed Early Register Release

Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
Trace Cache Sampling Filter

Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
Exploiting Coarse-Grain Verification Parallelism for Power-Efficient Fault Tolerance

Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
Reducing the Latency and Area Cost of Core Swapping through Shared Helper Engines

ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Energy and Performance Analysis of Mapping Parallel Multithreaded Tasks for An On-Chip Multi-Processor System

ICCD '05 Proceedings of the 2005 International Conference on Computer Design
RECAST: Boosting Tag Line Buffer Coverage in Low-Power High-Level Caches "for Free"

ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Load-Store Queue Management: an Energy-Efficient Design Based on a State-Filtering Mechanism.

ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Optimizing the Thermal Behavior of Subarrayed Data Caches

ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Reducing the Energy of Speculative Instruction Schedulers

ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation

ICCD '05 Proceedings of the 2005 International Conference on Computer Design
ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing

Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Balancing Resource Utilization to Mitigate Power Density in Processor Pipelines

Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
"Flea-flicker" Multipass Pipelining: An Alternative to the High-Power Out-of-Order Offense

Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
High-Performance, Power-Aware Distributed Computing for Scientific Applications

Computer
Formal Control Techniques for Power-Performance Management

IEEE Micro
Energy Awareness and Uncertainty in Microarchitecture-Level Design

IEEE Micro
Hardware-modulated parallelism in chip multiprocessors

ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
DRAMsim: a memory system simulator

ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Power-Efficient Error Tolerance in Chip Multiprocessors

IEEE Micro
Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency

IEEE Transactions on Computers
Hardware/software managed scratchpad memory for embedded system

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Simulation of Computer Architectures: Simulators, Benchmarks, Methodologies, and Recommendations

IEEE Transactions on Computers
Control Speculation for Energy-Efficient Next-Generation Superscalar Processors

IEEE Transactions on Computers
Compiler-directed high-level energy estimation and optimization

ACM Transactions on Embedded Computing Systems (TECS)
Power-performance considerations of parallel computing on chip multiprocessors

ACM Transactions on Architecture and Code Optimization (TACO)
Tolerating Cache-Miss Latency with Multipass Pipelines

IEEE Micro
Energy-Efficient Thread-Level Speculation

IEEE Micro
SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An automated design flow for 3D microarchitecture evaluation

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Optimal topology exploration for application-specific 3D architectures

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A system-level power-estimation methodology based on IP-level modeling, power-level adjustment, and power accumulation

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
PowerViP: Soc power estimation framework at transaction level

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A novel instruction scratchpad memory optimization method based on concomitance metric

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Finding optimal L1 cache configuration for embedded systems

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
SEA: fast power estimation for micro-architectures

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
HyPE: hybrid power estimation for IP-based programmable systems

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
An integrated performance and power model for superscalar processor designs

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Reducing leakage power in instruction cache using WDC for embedded processors

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Zero cost indexing for improved processor cache performance

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Compilers for leakage power reduction

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Thermal Trends in Emerging Technologies

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Thermal analysis of a 3D die-stacked high-performance microprocessor

GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
TOIGP: a new hierarchical depth occlusion

Proceedings of the 2006 ACM international conference on Virtual reality continuum and its applications
Simultaneously improving code size, performance, and energy in embedded processors

Proceedings of the conference on Design, automation and test in Europe: Proceedings
Automatic insertion of low power annotations in RTL for pipelined microprocessors

Proceedings of the conference on Design, automation and test in Europe: Proceedings
Microarchitectural floorplanning under performance and thermal tradeoff

Proceedings of the conference on Design, automation and test in Europe: Proceedings
FAST: Frequency-aware static timing analysis

ACM Transactions on Embedded Computing Systems (TECS)
Reducing NoC energy consumption through compiler-directed channel voltage scaling

Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation
Impact of virtual execution environments on processor energy consumption and hardware adaptation

Proceedings of the 2nd international conference on Virtual execution environments
Performance Models for Network Processor Design

IEEE Transactions on Parallel and Distributed Systems
Dynamic voltage scaling techniques for power efficient video decoding

Journal of Systems Architecture: the EUROMICRO Journal
Branchless cycle prediction for embedded processors

Proceedings of the 2006 ACM symposium on Applied computing
Modeling wire delay, area, power, and performance in a simulation infrastructure

IBM Journal of Research and Development
Systematic temperature sensor allocation and placement for microprocessors

Proceedings of the 43rd annual Design Automation Conference
Statistical sampling of microarchitecture simulation

ACM Transactions on Modeling and Computer Simulation (TOMACS)
Power-efficient instruction delivery through trace reuse

Proceedings of the 15th international conference on Parallel architectures and compilation techniques
SEED: scalable, efficient enforcement of dependences

Proceedings of the 15th international conference on Parallel architectures and compilation techniques
Throttling-Based Resource Management in High Performance Multithreaded Architectures

IEEE Transactions on Computers
Block-aware instruction set architecture

ACM Transactions on Architecture and Code Optimization (TACO)
A case for chip multiprocessors based on the data-driven multithreading model

International Journal of Parallel Programming
Stall cycle redistribution in a transparent fetch pipeline

Proceedings of the 2006 international symposium on Low power electronics and design
Energy-efficient dynamic instruction scheduling logic through instruction grouping

Proceedings of the 2006 international symposium on Low power electronics and design
Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture

Proceedings of the 2006 international symposium on Low power electronics and design
Synergistic temperature and energy management in GALS processor architectures

Proceedings of the 2006 international symposium on Low power electronics and design
Substituting associative load queue with simple hash tables in out-of-order microprocessors

Proceedings of the 2006 international symposium on Low power electronics and design
Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis

Proceedings of the 2006 international symposium on Low power electronics and design
Dynamic thermal management for MPEG-2 decoding

Proceedings of the 2006 international symposium on Low power electronics and design
Reducing power through compiler-directed barrier synchronization elimination

Proceedings of the 2006 international symposium on Low power electronics and design
Investigating cache energy and latency break-even points in high performance processors

MEDEA '06 Proceedings of the 2006 workshop on MEmory performance: DEaling with Applications, systems and architectures
Tartan: evaluating spatial computation for whole program execution

Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Software-based instruction caching for embedded processors

Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Adapting compilation techniques to enhance the packing of instructions into registers

CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Adaptive and flexible dictionary code compression for embedded applications

CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Entropy-based low power data TLB design

CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Improving the performance and power efficiency of shared helpers in CMPs

CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
High-level power analysis for multi-core chips

CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
The exigency of benchmark and compiler drift: designing tomorrow's processors with yesterday's tools

Proceedings of the 20th annual international conference on Supercomputing
Accurate memory data flow modeling in statistical simulation

Proceedings of the 20th annual international conference on Supercomputing
Design space exploration for multicore architectures: a power/performance/thermal view

Proceedings of the 20th annual international conference on Supercomputing
Evaluating trace cache energy efficiency

ACM Transactions on Architecture and Code Optimization (TACO)
Effective management of multiple configurable units using dynamic optimization

ACM Transactions on Architecture and Code Optimization (TACO)
The potential energy efficiency of vector acceleration

Proceedings of the 2006 ACM/IEEE conference on Supercomputing
Trace cache sampling filter

ACM Transactions on Computer Systems (TOCS)
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
DMDC: Delayed Memory Dependence Checking through Age-Based Filtering

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Power-efficient prefetching for embedded processors

ACM Transactions on Embedded Computing Systems (TECS)
The XTREM power and performance simulator for the Intel XScale core: Design and experiences

ACM Transactions on Embedded Computing Systems (TECS)
ALP: Efficient support for all levels of parallelism for complex media applications

ACM Transactions on Architecture and Code Optimization (TACO)
Conserving network processor power consumption by exploiting traffic variability

ACM Transactions on Architecture and Code Optimization (TACO)
Hybrid-scheduling for reduced energy consumption in high-performance processors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Active bank switching for temperature control of the register file in a microprocessor

Proceedings of the 17th ACM Great Lakes symposium on VLSI
Software power estimation using IPI(inter-prefetch interval) power model for advanced off-the-shelf processor

Proceedings of the 17th ACM Great Lakes symposium on VLSI
Using fine grain multithreading for energy efficient computing

Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming
Low-power tradeoffs for mobile computing applications: embedded processors versus custom computing kernels

ACM-SE 45 Proceedings of the 45th annual southeast regional conference
Multi-objective design space exploration of embedded systems

Journal of Embedded Computing - Low-power Embedded Systems
Integrating functional and power simulation in embedded systems design

Journal of Embedded Computing - Low-power Embedded Systems
Instruction buffering exploration for low energy embedded processors

Journal of Embedded Computing - Low-power Embedded Systems
Iterative compilation for energy reduction

Journal of Embedded Computing - Cache exploitation in embedded systems
Power and accuracy trade-offs in sound-based context recognition systems

Pervasive and Mobile Computing
Improving fairness, throughput and energy-efficiency on a chip multiprocessor through DVFS

ACM SIGARCH Computer Architecture News
Reducing non-deterministic loads in low-power caches via early cache set resolution

Microprocessors & Microsystems
Fast, accurate design space exploration of embedded systems memory configurations

Proceedings of the 2007 ACM symposium on Applied computing
Hybrid functional- and instruction-level power modeling for embedded and heterogeneous processor architectures

Journal of Systems Architecture: the EUROMICRO Journal
Exploiting program phase behavior for energy reduction on multi-configuration processors

Journal of Systems Architecture: the EUROMICRO Journal
Power model validation through thermal measurements

Proceedings of the 34th annual international symposium on Computer architecture
Thermal modeling and management of DRAM memory systems

Proceedings of the 34th annual international symposium on Computer architecture
ReCycle:: pipeline adaptation to tolerate process variation

Proceedings of the 34th annual international symposium on Computer architecture
Automated design of application specific superscalar processors: an analytical approach

Proceedings of the 34th annual international symposium on Computer architecture
Energy conservation policies for web servers

USITS'03 Proceedings of the 4th conference on USENIX Symposium on Internet Technologies and Systems - Volume 4
Addressing instruction fetch bottlenecks by using an instruction register file

Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Compiler-managed partitioned data caches for low power

Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Resource prediction for media stream decoding

Proceedings of the conference on Design, automation and test in Europe
Understanding voltage variations in chip multiprocessors using a distributed power-delivery network

Proceedings of the conference on Design, automation and test in Europe
Microarchitecture floorplanning for sub-threshold leakage reduction

Proceedings of the conference on Design, automation and test in Europe
Accurate temperature-dependent integrated circuit leakage power estimation is easy

Proceedings of the conference on Design, automation and test in Europe
Memory bank aware dynamic loop scheduling

Proceedings of the conference on Design, automation and test in Europe
Accurate and fast system-level power modeling: An XScale-based case study

ACM Transactions on Embedded Computing Systems (TECS) - Special Section LCTES'05
QUILT: a GUI-based integrated circuit floorplanning environment for computer architecture research and education

WCAE '05 Proceedings of the 2005 workshop on Computer architecture education: held in conjunction with the 32nd International Symposium on Computer Architecture
PSATSim: an interactive graphical superscalar architecture simulator for power and performance analysis

WCAE '06 Proceedings of the 2006 workshop on Computer architecture education: held in conjunction with the 33rd International Symposium on Computer Architecture
Cross-component energy management: Joint adaptation of processor and memory

ACM Transactions on Architecture and Code Optimization (TACO)
Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Compilation for compact power-gating controls

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Measuring performance, power, and temperature from real processors

Proceedings of the 2007 workshop on Experimental computer science
Analysis of dynamic voltage/frequency scaling in chip-multiprocessors

ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Towards a software approach to mitigate voltage emergencies

ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Power signal processing: a new perspective for power analysis and optimization

ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Resource area dilation to reduce power density in throughput servers

ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Power-aware operand delivery

ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Phase-aware adaptive hardware selection for power-efficient scientific computations

ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Measuring performance, power, and temperature from real processors

ecs'07 Experimental computer science on Experimental computer science
Softexplorer: estimating and optimizing the power and energy consumption of a C program for DSP applications

EURASIP Journal on Applied Signal Processing
Rapid energy estimation for hardware-software codesign using FPGAs

EURASIP Journal on Embedded Systems
Power deregulation: eliminating off-chip voltage regulation circuitry from embedded systems

CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Performance modeling for early analysis of multi-core systems

CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Cache leakage control mechanism for hard real-time systems

CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
A low power front-end for embedded processors using a block-aware instruction set

CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
SimWattch: Integrating Complete-System and User-Level Performance and Power Simulators

IEEE Micro
Scalable Dynamic Instruction Scheduler through Wake-Up Spatial Locality

IEEE Transactions on Computers
Speed versus Accuracy Trade-Offs in Microarchitectural Simulations

IEEE Transactions on Computers
A framework for system-level modeling and simulation of embedded systems architectures

EURASIP Journal on Embedded Systems
Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Investigating cache energy and latency break-even points in high performance processors

ACM SIGARCH Computer Architecture News
Synchronization coherence: A transparent hardware mechanism for cache coherence and fine-grained synchronization

Journal of Parallel and Distributed Computing
Memory Data Flow Modeling in Statistical Simulation for the Efficient Exploration of Microprocessor Design Spaces

IEEE Transactions on Computers
Optimal Power/Performance Pipeline Depth for SMT in Scaled Technologies

IEEE Transactions on Computers
Improving the performance of object-oriented languages with dynamic predication of indirect jumps

Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
Accurate and fast system-level power modeling: An XScale-based case study

ACM Transactions on Embedded Computing Systems (TECS)
Bus-aware microarchitectural floorplanning

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A unified methodology for power supply noise reduction in modern microarchitecture design

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Exploring power management in multi-core systems

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Software-cooperative power-efficient heterogeneous multi-core for media processing

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A partitioned instruction queue to reduce instruction wakeup energy

International Journal of High Performance Computing and Networking
High-performance and low-power VLIW cores for numerical computations

International Journal of High Performance Computing and Networking
Optimal pipeline depth with pipeline stage unification adoption

ACM SIGARCH Computer Architecture News - Special issue: ALPS '07---advanced low power systems
Power-efficient and scalable load/store queue design via address compression

Proceedings of the 2008 ACM symposium on Applied computing
The revolution inside the box

Communications of the ACM - Web science
Power management of variation aware chip multiprocessors

Proceedings of the 18th ACM Great Lakes symposium on VLSI
Low power microarchitecture with instruction reuse

Proceedings of the 5th conference on Computing frontiers
Compiler-directed frequency and voltage scaling for a multiple clock domain microarchitecture

Proceedings of the 5th conference on Computing frontiers
Profiling of symmetric-encryption algorithms for a novel biomedical-implant architecture

Proceedings of the 5th conference on Computing frontiers
Active storage revisited: the case for power and performance benefits for unstructured data processing applications

Proceedings of the 5th conference on Computing frontiers
An energy characterization platform for memory devices and energy-aware data compression for multilevel-cell flash memory

ACM Transactions on Design Automation of Electronic Systems (TODAES)
ILP-Based energy minimization techniques for banked memories

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Formulating and implementing profiling over adaptive ranges

ACM Transactions on Architecture and Code Optimization (TACO)
Addressing thermal nonuniformity in SMT workloads

ACM Transactions on Architecture and Code Optimization (TACO)
Instruction Reuse in SPEC, media and packet processing benchmarks: A comparative study of power, performance and related microarchitectural optimizations

Journal of Embedded Computing - Embeded Processors and Systems: Architectural Issues and Solutions for Emerging Applications
Destructive-read in embedded DRAM, impact on power consumption

Journal of Embedded Computing - Issues in embedded single-chip multicore architectures
Exploring power reduction options for a single-chip multiprocessor through system-level modeling

Journal of Embedded Computing - Issues in embedded single-chip multicore architectures
Software-directed combined cpu/link voltage scaling fornoc-based cmps

SIGMETRICS '08 Proceedings of the 2008 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors

Proceedings of the 2008 ACM SIGPLAN-SIGBED conference on Languages, compilers, and tools for embedded systems
Accurate and scalable simulation of network of heterogeneous sensor devices

Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
Early detection and bypassing of trivial operations to improve energy efficiency of processors

Microprocessors & Microsystems
A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies

ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors

ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Systematic approaches to understanding and evaluating design trade-offs

Journal of Systems and Software
Searching for resource-efficient programs: low-power pseudorandom number generators

Proceedings of the 10th annual conference on Genetic and evolutionary computation
Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency

Proceedings of the 45th annual Design Automation Conference
Application mapping for chip multiprocessors

Proceedings of the 45th annual Design Automation Conference
Federation: repurposing scalar cores for out-of-order instruction issue

Proceedings of the 45th annual Design Automation Conference
Automated hardware-independent scenario identification

Proceedings of the 45th annual Design Automation Conference
O2C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors

Proceedings of the 13th international symposium on Low power electronics and design
Frequency planning for multi-core processors under thermal constraints

Proceedings of the 13th international symposium on Low power electronics and design
Word-interleaved cache: an energy efficient data cache architecture

Proceedings of the 13th international symposium on Low power electronics and design
Full-system chip multiprocessor power evaluations using FPGA-based emulation

Proceedings of the 13th international symposium on Low power electronics and design
Impact of dynamic voltage and frequency scaling on the architectural vulnerability of GALS architectures

Proceedings of the 13th international symposium on Low power electronics and design
Thread fusion

Proceedings of the 13th international symposium on Low power electronics and design
Power-efficient clustering via incomplete bypassing

Proceedings of the 13th international symposium on Low power electronics and design
On the effectiveness of phase based regression models to trade power and performance using dynamic processor adaptation

Journal of Systems Architecture: the EUROMICRO Journal
Thermal monitoring mechanisms for chip multiprocessors

ACM Transactions on Architecture and Code Optimization (TACO)
Distilling the essence of proprietary workloads into miniature benchmarks

ACM Transactions on Architecture and Code Optimization (TACO)
An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures

The Journal of Supercomputing
Power-Directed Software Prefetching Algorithm with Dynamic Voltage Scaling

ICCS '07 Proceedings of the 7th international conference on Computational Science, Part IV: ICCS 2007
Power-Aware Software Prefetching

ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
Automatic Power Model Generation for Sensor Network Simulator

ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
Efficient code caching to improve performance and energy consumption for java applications

CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Profiling of lossless-compression algorithms for a novel biomedical-implant architecture

CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Cache-aware optimization of BAN applications

CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Methodology for multi-granularity embedded processor power model generation for an ESL design flow

CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Application Domain Specific Embedded FPGAs for Flexible ISA-Extension of ASIPs

Journal of Signal Processing Systems
Multi-optimization power management for chip multiprocessors

Proceedings of the 17th international conference on Parallel architectures and compilation techniques
An adaptive resource partitioning algorithm for SMT processors

Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Meeting points: using thread criticality to adapt multicore hardware to parallel regions

Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Optimizing CAM-based instruction cache designs for low-power embedded systems

Journal of Systems Architecture: the EUROMICRO Journal
A component infrastructure for performance and power modeling of parallel scientific applications

Proceedings of the 2008 compFrame/HPC-GECO workshop on Component based high performance
Three-dimensional Integrated Circuit Design

Three-dimensional Integrated Circuit Design
Ternary CAM power and delay model: extensions and uses

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
L-CBF: a low-power, fast counting bloom filter architecture

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
GOP-level dynamic thermal management in MPEG-2 decoding

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Case study of reliability-aware and low-power design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Finding Stress Patterns in Microprocessor Workloads

HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors

HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines

HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic

HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Specializing Cache Structures for High Performance and Energy Conservation in Embedded Systems

Transactions on High-Performance Embedded Architectures and Compilers I
Thermal Design Space Exploration of 3D Die Stacked Multi-core Processors Using Geospatial-Based Predictive Models

Proceedings of the 2009 SPEC Benchmark Workshop on Computer Performance Evaluation and Benchmarking
Power-Aware Design via Micro-architectural Link to Implementation

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Using age registers for a simple load-store queue filtering

Journal of Systems Architecture: the EUROMICRO Journal
StreamRay: a stream filtering architecture for coherent ray tracing

Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Zero loads: canceling load requests by tracking zero values

Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture
A framework for predictive dynamic temperature management of microprocessor systems

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Integrated code and data placement in two-dimensional mesh based chip multiprocessors

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Temperature aware task sequencing and voltage scaling

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Thermal optimization in multi-granularity multi-core floorplanning

Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A criticality-driven microarchitectural three dimensional (3D) floorplanner

Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Memory subsystem simulation in software TLM/T models

Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Superscalar architecture design for high performance DSP operations

Microprocessors & Microsystems
Exploiting selective instruction reuse and value prediction in a superscalar architecture

Journal of Systems Architecture: the EUROMICRO Journal
Facelift: Hiding and slowing down aging in multicores

Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach

Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
NBTI tolerant microarchitecture design in the presence of process variation

Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
EVAL: Utilizing processors with variation-induced timing errors

Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Efficient Method to Generate an Energy Efficient Schedule Using Operation Shuffling

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs

IEICE - Transactions on Information and Systems
A Dynamic Control Mechanism for Pipeline Stage Unification by Identifying Program Phases

IEICE - Transactions on Information and Systems
Playing the trade-off game: Architecture exploration using Coffeee

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Central vs. distributed dynamic thermal management for multi-core processors: which one is better?

Proceedings of the 19th ACM Great Lakes symposium on VLSI
Fast switching of threads between cores

ACM SIGOPS Operating Systems Review
Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches

Transactions on High-Performance Embedded Architectures and Compilers II
Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems

Transactions on High-Performance Embedded Architectures and Compilers II
DSiMCluster: A Simulation Model for Efficient Memory Analysis Experiments of DSM Clusters

Simulation
Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE)

Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
EMPIRE: Empirical power/area/timing models for register files

Microprocessors & Microsystems
Two-Level Dictionary Code Compression: A New Scheme to Improve Instruction Code Density of Embedded Applications

Proceedings of the 7th annual IEEE/ACM International Symposium on Code Generation and Optimization
An energy-efficient instruction scheduler design with two-level shelving and adaptive banking

Journal of Computer Science and Technology
Multi-mechanism reliability modeling and management in dynamic systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Polaris: a system-level roadmapping toolchain for on-chip interconnection networks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Evaluating the impact of job scheduling and power management on processor lifetime for chip multiprocessors

Proceedings of the eleventh international joint conference on Measurement and modeling of computer systems
Dynamic MIPS rate stabilization in out-of-order processors

Proceedings of the 36th annual international symposium on Computer architecture
Temperature-constrained power control for chip multiprocessors with online model estimation

Proceedings of the 36th annual international symposium on Computer architecture
Power Consumption of GPUs from a Software Perspective

ICCS '09 Proceedings of the 9th International Conference on Computational Science: Part I
Energy-performance Exploration of a CGA-based SDR Processor

Journal of Signal Processing Systems
Instruction-Level Fault Tolerance Configurability

Journal of Signal Processing Systems
Energy characterization of mobile devices and applications using power-thermal benchmarks

Microelectronics Journal
Adapting application execution in CMPs using helper threads

Journal of Parallel and Distributed Computing
Real time power estimation and thread scheduling via performance counters

ACM SIGARCH Computer Architecture News
Towards a network-device unified framework for power-aware wireless applications

Proceedings of the 2009 International Conference on Wireless Communications and Mobile Computing: Connecting the World Wirelessly
Exploring the limits of early register release: Exploiting compiler analysis

ACM Transactions on Architecture and Code Optimization (TACO)
Predict and act: dynamic thermal management for multi-core processors

Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Dynamic thermal management using thin-film thermoelectric cooling

Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Way-tagged cache: an energy-efficient L2 cache architecture under write-through policy

Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Cooperative shared resource access control for low-power chip multiprocessors

Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
End-to-end validation of architectural power models

Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Energy-efficient register caching with compiler assistance

ACM Transactions on Architecture and Code Optimization (TACO)
The Design and Evaluation of a Selective Way Based Trace Cache

APPT '09 Proceedings of the 8th International Symposium on Advanced Parallel Processing Technologies
Temperature reduction analysis in Sentry Tag cache systems

Proceedings of the 10th workshop on MEmory performance: DEaling with Applications, systems and architecture
SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems

CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Spectral techniques for high-resolution thermal characterization with limited sensor data

Proceedings of the 46th Annual Design Automation Conference
Dynamic thermal management via architectural adaptation

Proceedings of the 46th Annual Design Automation Conference
Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack

Proceedings of the 46th Annual Design Automation Conference
A DVS-based pipelined reconfigurable instruction memory

Proceedings of the 46th Annual Design Automation Conference
Efficient program scheduling for heterogeneous multi-core processors

Proceedings of the 46th Annual Design Automation Conference
Negotiation of security services: a multi-criteria decision approach

WESS '09 Proceedings of the 4th Workshop on Embedded Systems Security
Run-time selection of security algorithms for networked devices

Proceedings of the 5th ACM symposium on QoS and security for wireless and mobile networks
Adaptive scratch pad memory management for dynamic behavior of multimedia applications

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multiscale thermal analysis for nanometer-scale integrated circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using data compression for increasing memory system utilization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ePRO-MP: A tool for profiling and optimizing energy and performance of mobile multiprocessor applications

Scientific Programming - Software Development for Multi-core Computing Systems
Energy simulation of embedded XScale systems with XEEMU

Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
Into the wild: studying real user activity patterns to guide power optimizations for mobile architectures

Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Reducing peak power with a table-driven adaptive processor core

Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
The BubbleWrap many-core: popping cores for sequential acceleration

Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures

Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
REMiS: run-time energy minimization scheme in a reconfigurable processor with dynamic power-gated instruction set

Proceedings of the 2009 International Conference on Computer-Aided Design
A hybrid local-global approach for multi-core thermal management

Proceedings of the 2009 International Conference on Computer-Aided Design
Energy-optimal dynamic thermal management for green computing

Proceedings of the 2009 International Conference on Computer-Aided Design
Architecture level design space exploration of superscalar processor for multimedia applications

SPECTS'09 Proceedings of the 12th international conference on Symposium on Performance Evaluation of Computer & Telecommunication Systems
Thermal analysis of multiprocessor SoC applications by simulation and verification

ACM Transactions on Design Automation of Electronic Systems (TODAES)
An energy efficient and high security watermarking mechanism based on DS-CDMA

ICME'09 Proceedings of the 2009 IEEE international conference on Multimedia and Expo
Quality-of-service and error control techniques for mesh-based network-on-chip architectures

Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach

Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
A cross-layer approach to heterogeneity and reliability

MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Power and distortion optimization for pervasive video coding

IEEE Transactions on Circuits and Systems for Video Technology
Utilizing predictors for efficient thermal management in multiprocessor SoCs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast and accurate prediction of the steady-state throughput of multicore processors under thermal constraints

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ReSPIR: a response surface-based Pareto iterative refinement for application-specific design space exploration

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Mitigating the impact of variability on chip-multiprocessor power and performance

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Characterizing processor thermal behavior

Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems
Virtualized and flexible ECC for main memory

Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems
Chameleon: Virtualizing idle acceleration cores of a heterogeneous multicore processor for caching and prefetching

ACM Transactions on Architecture and Code Optimization (TACO)
Network/hardware cross-layer evaluation for ROHC and packet aggregation on wireless mesh networks

Wireless Networks
Rapid design space exploration using legacy design data and technology scaling trend

Integration, the VLSI Journal
On-chip sensor-driven efficient thermal profile estimation algorithms

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Compiler directed network-on-chip reliability enhancement for chip multiprocessors

Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Evaluation of parameter sensitivity for portable embedded systems through evolutionary techniques

GECCO'03 Proceedings of the 2003 international conference on Genetic and evolutionary computation: PartII
Leveraging high performance data cache techniques to save power in embedded systems

HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
Applying decay to reduce dynamic power in set-associative caches

HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
Reducing branch misprediction penalties via adaptive pipeline scaling

HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
Sunflower: full-system, embedded, microarchitecture evaluation

HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
Early-stage definition of LPX: a low power issue-execute processor

PACS'02 Proceedings of the 2nd international conference on Power-aware computer systems
Dynamic tag-check omission: a low power instruction cache architecture exploiting execution footprints

PACS'02 Proceedings of the 2nd international conference on Power-aware computer systems
Multi-processor computer system having low power consumption

PACS'02 Proceedings of the 2nd international conference on Power-aware computer systems
Modeling of DRAM power control policies using deterministic and stochastic Petri nets

PACS'02 Proceedings of the 2nd international conference on Power-aware computer systems
Instruction balance and its relation to program energy consumption

LCPC'01 Proceedings of the 14th international conference on Languages and compilers for parallel computing
Dynamic voltage and frequency scaling for scientific applications

LCPC'01 Proceedings of the 14th international conference on Languages and compilers for parallel computing
Improving chip multiprocessor reliability through code replication

Computers and Electrical Engineering
Dynamic register-renaming scheme for reducing power-density and temperature

Proceedings of the 2010 ACM Symposium on Applied Computing
A study of energy saving in customizable processors

SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Design methodology for software radio systems

SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Compiler support for dynamic pipeline scaling

EUC'07 Proceedings of the 2007 international conference on Embedded and ubiquitous computing
Efficient message management in tiled CMP architectures using a heterogeneous interconnection network

HiPC'07 Proceedings of the 14th international conference on High performance computing
Reuse distance based cache leakage control

HiPC'07 Proceedings of the 14th international conference on High performance computing
Performance evaluation of compiler controlled power saving scheme

ISHPC'05/ALPS'06 Proceedings of the 6th international symposium on high-performance computing and 1st international conference on Advanced low power systems
A model to exploit power-performance efficiency in superscalar processors via structure resizing

Proceedings of the 20th symposium on Great lakes symposium on VLSI
Power-efficient, reliable microprocessor architectures: modeling and design methods

Proceedings of the 20th symposium on Great lakes symposium on VLSI
A virtual platform environment for exploring power, thermal and reliability management control strategies in high-performance multicores

Proceedings of the 20th symposium on Great lakes symposium on VLSI
Thermal-aware voltage droop compensation for multi-core architectures

Proceedings of the 20th symposium on Great lakes symposium on VLSI
Performance and energy efficient cache migrationapproach for thermal management in embedded systems

Proceedings of the 20th symposium on Great lakes symposium on VLSI
A self-adaptive scheduler for asymmetric multi-cores

Proceedings of the 20th symposium on Great lakes symposium on VLSI
A novel multi-objective instruction synthesis flow for application-specific instruction set processors

Proceedings of the 20th symposium on Great lakes symposium on VLSI
COFFEE: compiler framework for energy-aware exploration

HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
Interval-based models for run-time DVFS orchestration in superscalar processors

Proceedings of the 7th ACM international conference on Computing frontiers
Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units

Proceedings of the 7th ACM international conference on Computing frontiers
WHOLE: a low energy I-cache with separate way history

ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Deterministic clock gating to eliminate wasteful activity due to wrong-path instructions in out-of-order superscalar processors¹

ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Rapid early-stage microarchitecture design using predictive models

ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
The impact of liquid cooling on 3D multi-core processors

ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Adaptive L2 cache for chip multiprocessors

Euro-Par'07 Proceedings of the 2007 conference on Parallel processing
Virtual machine power metering and provisioning

Proceedings of the 1st ACM symposium on Cloud computing
WattApp: an application aware power meter for shared data centers

Proceedings of the 7th international conference on Autonomic computing
Chip multiprocessor based on data-driven multithreading model

International Journal of High Performance Systems Architecture
Multi-processor system-on-chip design space exploration based on multi-level modeling techniques

SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
WiDGET: Wisconsin decoupled grid execution tiles

Proceedings of the 37th annual international symposium on Computer architecture
Forwardflow: a scalable core for power-constrained CMPs

Proceedings of the 37th annual international symposium on Computer architecture
Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis

Proceedings of the 37th annual international symposium on Computer architecture
An integrated GPU power and performance model

Proceedings of the 37th annual international symposium on Computer architecture
Necromancer: enhancing system throughput by animating dead cores

Proceedings of the 37th annual international symposium on Computer architecture
Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors

Proceedings of the 37th annual international symposium on Computer architecture
A High-level Microprocessor Power Modeling Technique Based on Event Signatures

Journal of Signal Processing Systems
On the latency and energy of checkpointed superscalar register alias tables

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Quantifying and coping with parametric variations in 3D-stacked microarchitectures

Proceedings of the 47th Design Automation Conference
SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy

Proceedings of the 47th Design Automation Conference
Distributed task migration for thermal management in many-core systems

Proceedings of the 47th Design Automation Conference
Thermal aware task sequencing on embedded processors

Proceedings of the 47th Design Automation Conference
A framework for optimizing thermoelectric active cooling systems

Proceedings of the 47th Design Automation Conference
Performance and power modeling in a multi-programmed multi-core environment

Proceedings of the 47th Design Automation Conference
Power-aware BTB for modern processors

Computers and Electrical Engineering
Thread-management techniques to maximize efficiency in multicore and simultaneous multithreaded microprocessors

ACM Transactions on Architecture and Code Optimization (TACO)
Eliminating voltage emergencies via software-guided code transformations

ACM Transactions on Architecture and Code Optimization (TACO)
Power-efficient variation-aware photonic on-chip network management

Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Exploring custom instruction synthesis for application-specific instruction set processors with multiple design objectives

Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Peak power modeling for data center servers with switched-mode power supplies

Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Post-silicon power characterization using thermal infrared emissions

Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Exploiting address compression and heterogeneous interconnects for efficient message management in tiled CMPs

Journal of Systems Architecture: the EUROMICRO Journal
Generating power-hungry test programs for power-aware validation of pipelined processors

SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
System-level max power (SYMPO): a systematic approach for escalating system-level power consumption using synthetic benchmarks

Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Scalable thread scheduling and global power management for heterogeneous many-core architectures

Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Criticality-driven superscalar design space exploration

Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Efficient runahead threads

Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Energy efficient speculative threads: dynamic thread allocation in Same-ISA heterogeneous multicore systems

Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Energy-efficient parallel software for mobile hand-held devices

HotPar'09 Proceedings of the First USENIX conference on Hot topics in parallelism
Packet transmission policies for battery operated wireless sensor networks

Frontiers of Computer Science in China
An overview of achieving energy efficiency in on-chip networks

International Journal of Communication Networks and Distributed Systems
Register-relocation: a thermal-aware renaming method for reducing temperature of a register file

ACM SIGAPP Applied Computing Review
Multicore soft error rate stabilization using adaptive dual modular redundancy

Proceedings of the Conference on Design, Automation and Test in Europe
Optimization of an on-chip active cooling system based on thin-film thermoelectric coolers

Proceedings of the Conference on Design, Automation and Test in Europe
An integrated framework for joint design space exploration of microarchitecture and circuits

Proceedings of the Conference on Design, Automation and Test in Europe
Energy-performance design space exploration in SMT architectures exploiting selective load value predictions

Proceedings of the Conference on Design, Automation and Test in Europe
DEW: a fast level 1 cache simulation approach for embedded processors with FIFO replacement policy

Proceedings of the Conference on Design, Automation and Test in Europe
Process variation and temperature-aware reliability management

Proceedings of the Conference on Design, Automation and Test in Europe
Clock gating approaches by IOEX graphs and cluster efficiency plots

Proceedings of the Conference on Design, Automation and Test in Europe
A reconfigurable cache memory with heterogeneous banks

Proceedings of the Conference on Design, Automation and Test in Europe
Multiplexed redundant execution: a technique for efficient fault tolerance in chip multiprocessors

Proceedings of the Conference on Design, Automation and Test in Europe
A self-adaptive system architecture to address transistor aging

Proceedings of the Conference on Design, Automation and Test in Europe
An event-guided approach to reducing voltage noise in processors

Proceedings of the Conference on Design, Automation and Test in Europe
Energy efficient multiprocessor task scheduling under input-dependent variation

Proceedings of the Conference on Design, Automation and Test in Europe
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration

Proceedings of the Conference on Design, Automation and Test in Europe
Hardware/software co-design architecture for thermal management of chip multiprocessors

Proceedings of the Conference on Design, Automation and Test in Europe
Exploiting narrow-width values for thermal-aware register file designs

Proceedings of the Conference on Design, Automation and Test in Europe
Distributed peak power management for many-core architectures

Proceedings of the Conference on Design, Automation and Test in Europe
Accurate direct and indirect on-chip temperature sensing for efficient dynamic thermal management

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Characterization and exploitation of narrow-width loads: the narrow-width cache approach

CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
Power aware SID-based simulator for embedded multicore DSP subsystems

CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Design exploration of hybrid caches with disparate memory technologies

ACM Transactions on Architecture and Code Optimization (TACO)
Federation: Boosting per-thread performance of throughput-oriented manycore architectures

ACM Transactions on Architecture and Code Optimization (TACO)
Parametric timing analysis and its application to dynamic voltage scaling

ACM Transactions on Embedded Computing Systems (TECS)
CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors

Proceedings of the 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis
On improving performance and energy profiles of sparse scientific applications

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Conjugate gradient sparse solvers: performance-power characteristics

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Empowering a helper cluster through data-width aware instruction selection policies

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Exploiting unbalanced thread scheduling for energy and performance on a CMP of SMT processors

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Improved on-chip router analytical power and area modeling

Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Runtime temperature-based power estimation for optimizing throughput of thermal-constrained multi-core processors

Proceedings of the 2010 Asia and South Pacific Design Automation Conference
High level event driven thermal estimation for thermal aware task allocation and scheduling

Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Hybrid dynamic energy and thermal management in heterogeneous embedded multiprocessor SoCs

Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Cool and save: cooling aware dynamic workload scheduling in multi-socket CPU systems

Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Floorplanning for low power IC design considering temperature variations

Microelectronics Journal
Erasing Core Boundaries for Robust and Configurable Performance

MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors

MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches

MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
A Predictive Model for Dynamic Microarchitectural Adaptivity Control

MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Adaptive and Speculative Slack Simulations of CMPs on CMPs

MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Automated empirical tuning of scientific codes for performance and power consumption

Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers
A precise high-level power consumption model for embedded systems software

EURASIP Journal on Embedded Systems
A formal model for performance and energy evaluation of embedded systems

EURASIP Journal on Embedded Systems - Special issue on networked embedded systems for energy management and buildings
Fine-grained DVFS using on-chip regulators

ACM Transactions on Architecture and Code Optimization (TACO)
Kernel Fusion: An Effective Method for Better Power Efficiency on Multithreaded GPU

GREENCOM-CPSCOM '10 Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing
Low Power Design for a Multi-core Multi-thread Microprocessor

GREENCOM-CPSCOM '10 Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing
A System-Level Model for Runtime Power Estimation on Mobile Devices

GREENCOM-CPSCOM '10 Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing
On Profiling the Energy Consumption of Distributed Simulations: A Case Study

GREENCOM-CPSCOM '10 Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing
Designing Energy Efficient Communication Runtime Systems for Data Centric Programming Models

GREENCOM-CPSCOM '10 Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing
FILESPPA: Fast Instruction Level Embedded System Power and Performance Analyzer

Microprocessors & Microsystems
WCET analysis of modern processors using multi-criteria optimisation

Empirical Software Engineering
Study of energy and performance of space-time decoding systems in concatenation with turbo decoding

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient synchronization for embedded on-chip multiprocessors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wake-up logic optimizations through selective match and wakeup range limitation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hotspot: acompact thermal modeling methodology for early-stage VLSI design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architectural enhancements for network congestion control applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Instruction buffering for nested loops in low-power design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploiting statistical information for implementation of instruction scratchpad memory in embedded system

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-efficient dynamic instruction scheduling logic through instruction grouping

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the exploitation of narrow-width values for improving register file reliability

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The structural simulation toolkit

ACM SIGMETRICS Performance Evaluation Review - Special issue on the 1st international workshop on performance modeling, benchmarking and simulation of high performance computing systems (PMBS 10)
A framework for architecture-level power, area, and thermal simulation and its application to network-on-chip design exploration

ACM SIGMETRICS Performance Evaluation Review - Special issue on the 1st international workshop on performance modeling, benchmarking and simulation of high performance computing systems (PMBS 10)
DCG: deterministic clock-gating for low-power microprocessor design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Global productiveness propagation: a code optimization technique to speculatively prune useless narrow computations

Proceedings of the 2011 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Exploiting dynamic micro-architecture usage in gate sizing

Microprocessors & Microsystems
The shape of the processor design space and its implications for early stage explorations

ACMOS'05 Proceedings of the 7th WSEAS international conference on Automatic control, modeling and simulation
Green secure processors: towards power-efficient secure processor design

Transactions on computational science X
A fine-grained runtime power/performance optimization method for processors with adaptive pipeline depth

Journal of Computer Science and Technology
Power delivery design for 3-D ICs using different through-silicon via (TSV) technologies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A multi-granularity power modeling methodology for embedded processors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A framework for correction of multi-bit soft errors in L2 caches based on redundancy

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
EnerJ: approximate data types for safe and general low-power computation

Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
Modeling program resource demand using inherent program characteristics

Proceedings of the ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems
Coordinating processor and main memory for efficientserver power control

Proceedings of the international conference on Supercomputing
Optimizing throughput/power trade-offs in hardware transactional memory using DVFS and intelligent scheduling

Proceedings of the international conference on Supercomputing
Predictive coordination of multiple on-chip resources for chip multiprocessors

Proceedings of the international conference on Supercomputing
Self-constructive high-rate system energy modeling for battery-powered mobile systems

MobiSys '11 Proceedings of the 9th international conference on Mobile systems, applications, and services
CRIB: consolidated rename, issue, and bypass

Proceedings of the 38th annual international symposium on Computer architecture
Rebound: scalable checkpointing for coherent shared memory

Proceedings of the 38th annual international symposium on Computer architecture
Adaptive granularity memory systems: a tradeoff between storage efficiency and throughput

Proceedings of the 38th annual international symposium on Computer architecture
Fighting fire with fire: modeling the datacenter-scale effects of targeted superlattice thermal management

Proceedings of the 38th annual international symposium on Computer architecture
Scalable power control for many-core architectures running multi-threaded applications

Proceedings of the 38th annual international symposium on Computer architecture
A study on factors influencing power consumption in multithreaded and multicore CPUs

WSEAS Transactions on Computers
Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigation

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Modeling program resource demand using inherent program characteristics

ACM SIGMETRICS Performance Evaluation Review - Performance evaluation review
Evaluation of dynamic voltage and frequency scaling for stream programs

Proceedings of the 8th ACM International Conference on Computing Frontiers
Eliminating energy of same-content-cell-columns of on-chip SRAM arrays

Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Automated di/dt stressmark generation for microprocessor power delivery networks

Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Software energy estimation based on statistical characterization of intermediate compilation code

Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Thread shuffling: combining DVFS and thread migration toreduce energy consumptions for multi-core systems

Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
NoC frequency scaling with flexible-pipeline routers

Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Maintaining performance on power gating of microprocessor functional units by using a predictive pre-wakeup strategy

ACM Transactions on Architecture and Code Optimization (TACO)
Improved post-silicon power modeling using AC lock-in techniques

Proceedings of the 48th Design Automation Conference
Throughput maximization for periodic real-time systems under the maximal temperature constraint

Proceedings of the 48th Design Automation Conference
Device modeling and system simulation of nanophotonic on-chip networks for reliability, power and performance

Proceedings of the 48th Design Automation Conference
EFFEX: an embedded processor for computer vision based feature extraction

Proceedings of the 48th Design Automation Conference
Evolutionary computation techniques for intrusion detection in mobile ad hoc networks

Computer Networks: The International Journal of Computer and Telecommunications Networking
Investigating energy and security trade-offs in the classroom with the atom LEAP testbed

CSET'11 Proceedings of the 4th conference on Cyber security experimentation and test
Thermal-aware floorplan schemes for reliable 3D multi-core processors

ICCSA'11 Proceedings of the 2011 international conference on Computational science and its applications - Volume Part II
A survey on energy-efficient data management

ACM SIGMOD Record
Color-Aware Instructions for Embedded Superscalar Processors

Journal of Signal Processing Systems
A unified approach to eliminate memory accesses early

CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
Architecting processors to allow voltage/reliability tradeoffs

CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
System-level power and timing variability characterization to compute thermal guarantees

CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
HC-Sim: a fast and exact l1 cache simulator with scratchpad memory co-simulation support

CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Layered Green Performance Indicators

Future Generation Computer Systems
Efficient co-simulation framework enhancing system-level power estimation for a platform-based SoC design

Microelectronics Journal
Architecture extensions for efficient management of scratch-pad memory

PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
MAximum Multicore POwer (MAMPO): an automatic multithreaded synthetic power virus generation framework for multicore systems

Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis
The Survey and Future Evolution of Green Computing

GREENCOM '11 Proceedings of the 2011 IEEE/ACM International Conference on Green Computing and Communications
Predictive Model-Based Thermal Management for Network Applications

Proceedings of the 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems
Compiler control power saving scheme for multi core processors

LCPC'05 Proceedings of the 18th international conference on Languages and Compilers for Parallel Computing
Exploiting video stream similarity for energy-efficient decoding

MMM'07 Proceedings of the 13th International conference on Multimedia Modeling - Volume Part II
Bahurupi: A polymorphic heterogeneous multi-core architecture

ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
Reducing the branch power cost in embedded processors through static scheduling, profiling and superblock formation

ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
An architectural leakage power reduction method for instruction cache in ultra deep submicron microprocessors

ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
The Java Virtual Machine in retargetable, high-performance instruction set simulation

Proceedings of the 9th International Conference on Principles and Practice of Programming in Java
Dynamic dictionary-based data compression for level-1 caches

ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
Estimating energy consumption for an MPSoC architectural exploration

ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
PASCOM: power model for supercomputers

ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
Power-Aware instruction scheduling

EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
Selective word reading for high performance and low power processor

Proceedings of the 2011 ACM Symposium on Research in Applied Computation
The design space of CMP vs. SMT for high performance embedded processor

ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Power consumption analysis of embedded multimedia application

ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Exploiting register-usage for saving register-file energy in embedded processors

EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
Characterizing the performance and energy attributes of scientific simulations

ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part I
Saving register-file leakage power by monitoring instruction sequence in ROB

EUC'06 Proceedings of the 2006 international conference on Emerging Directions in Embedded and Ubiquitous Computing
Co-optimization of performance and power in a superscalar processor design

EUC'06 Proceedings of the 2006 international conference on Emerging Directions in Embedded and Ubiquitous Computing
Beyond basic region caching: specializing cache structures for high performance and energy conservation

HiPEAC'05 Proceedings of the First international conference on High Performance Embedded Architectures and Compilers
Invited talk: in-house tools for low-power embedded systems

ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
Full-chip runtime error-tolerant thermal estimation and prediction for practical thermal management

Proceedings of the International Conference on Computer-Aided Design
Reliability, thermal, and power modeling and optimization

Proceedings of the International Conference on Computer-Aided Design
Design space navigation for neighboring power-performance efficient microprocessor configurations

ARCS'05 Proceedings of the 18th international conference on Architecture of Computing Systems conference on Systems Aspects in Organic and Pervasive Computing
Value compression for efficient computation

Euro-Par'05 Proceedings of the 11th international Euro-Par conference on Parallel Processing
Improving instruction delivery with a block-aware ISA

Euro-Par'05 Proceedings of the 11th international Euro-Par conference on Parallel Processing
Compiler analysis and supports for leakage power reduction on microprocessors

LCPC'02 Proceedings of the 15th international conference on Languages and Compilers for Parallel Computing
Exploiting media stream similarity for energy-efficient decoding and resource prediction

ACM Transactions on Embedded Computing Systems (TECS)
Power-aware branch logic: a hardware based technique for filtering access to branch logic

SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Offline phase analysis and optimization for multi-configuration processors

SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Hardware cost estimation for application-specific processor design

SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
A power-efficient and scalable load-store queue design

PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Dynamic instruction cascading on GALS microprocessors

PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Power reduction of superscalar processor functional units by resizing adder-width

PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
CRAM: coded registers for amplified multiporting

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Complementing user-level coarse-grain parallelism with implicit speculative parallelism

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Runtime biased pointer reuse analysis and its application to energy efficiency

PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
Exploring the potential of architecture-level power optimizations

PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
Coupled power and thermal simulation with active cooling

PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
TSV-constrained micro-channel infrastructure design for cooling stacked 3D-ICs

Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Energy-Effective instruction fetch unit for wide issue processors

ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Architectural enhancements for color image and video processing on embedded systems

ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Cache leakage management for multi-programming workloads

ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Low-overhead core swapping for thermal management

PACS'04 Proceedings of the 4th international conference on Power-Aware Computer Systems
Energy-aware data prefetching for general-purpose programs

PACS'04 Proceedings of the 4th international conference on Power-Aware Computer Systems
Dynamic processor throttling for power efficient computations

PACS'04 Proceedings of the 4th international conference on Power-Aware Computer Systems
Hybrid functional and instruction level power modeling for embedded processors

SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Memory architecture evaluation for video encoding on enhanced embedded processors

SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Impact of array data flow analysis on the design of energy-efficient circuits

PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A technique to reduce static and dynamic power of functional units in high-performance processors

PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Compiler directed issue queue energy reduction

Transactions on High-Performance Embedded Architectures and Compilers IV
Microvisor: a runtime architecture for thermal management in chip multiprocessors

Transactions on High-Performance Embedded Architectures and Compilers IV
Finding extreme behaviors in microprocessor workloads

Transactions on High-Performance Embedded Architectures and Compilers IV
Maestro: orchestrating lifetime reliability in chip multiprocessors

HiPEAC'10 Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers
MLP-Aware instruction queue resizing: the key to power-efficient performance

ARCS'10 Proceedings of the 23rd international conference on Architecture of Computing Systems
Balancing Programmability and Silicon Efficiency of Heterogeneous Multicore Architectures

ACM Transactions on Embedded Computing Systems (TECS)
Reliability-aware platform optimization for 3D chip multi-processors

The Journal of Supercomputing
An efficient power estimation methodology for complex RISC processor-based platforms

Proceedings of the great lakes symposium on VLSI
ADAM: an efficient data management mechanism for hybrid high and ultra-low voltage operation caches

Proceedings of the great lakes symposium on VLSI
Evaluating and modeling power consumption of multi-core processors

Proceedings of the 3rd International Conference on Future Energy Systems: Where Energy, Computing and Communication Meet
DMA-circular: an enhanced high level programmable DMA controller for optimized management of on-chip local memories

Proceedings of the 9th conference on Computing Frontiers
Studying the impact of application-level optimizations on the power consumption of multi-core architectures

Proceedings of the 9th conference on Computing Frontiers
Processor energy characterization for compiler-assisted software energy reduction

Journal of Electrical and Computer Engineering
A Variability-Aware Robust Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints

ACM Transactions on Embedded Computing Systems (TECS)
SEProf: A high-level software energy profiling tool for an embedded processor enabling power management functions

Journal of Systems and Software
A hybrid and adaptive model for predicting register file and SRAM power using a reference design

Proceedings of the 49th Annual Design Automation Conference
An information-theoretic framework for optimal temperature sensor allocation and full-chip thermal monitoring

Proceedings of the 49th Annual Design Automation Conference
Auto-tuning for energy usage in scientific applications

Euro-Par'11 Proceedings of the 2011 international conference on Parallel Processing - Volume 2
Energy storage in datacenters: what, where, and how much?

Proceedings of the 12th ACM SIGMETRICS/PERFORMANCE joint international conference on Measurement and Modeling of Computer Systems
Instruction-based energy estimation methodology for asymmetric manycore processor simulations

Proceedings of the 5th International ICST Conference on Simulation Tools and Techniques
SST + gem5 = a scalable simulation infrastructure for high performance computing

Proceedings of the 5th International ICST Conference on Simulation Tools and Techniques
UniFI: leveraging non-volatile memories for a unified fault tolerance and idle power management technique

Proceedings of the 26th ACM international conference on Supercomputing
Thermal-aware sampling in architectural simulation

Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Something old and something new: P-states can borrow microarchitecture techniques too

Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Reducing L1 caches power by exploiting software semantics

Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
A defect-tolerant accelerator for emerging high-performance applications

Proceedings of the 39th Annual International Symposium on Computer Architecture
Power Modeling and Characterization of Computing Devices: A Survey

Foundations and Trends in Electronic Design Automation
Multi-level simultaneous multithreading scheduling to reduce the temperature of register files

Concurrency and Computation: Practice & Experience
Adaptive dynamic frequency scaling for thermal-aware 3d multi-core processors

ICCSA'12 Proceedings of the 12th international conference on Computational Science and Its Applications - Volume Part IV
Empowering developers to estimate app energy consumption

Proceedings of the 18th annual international conference on Mobile computing and networking
A systematic methodology for reliability improvements on SoC-based software defined radio systems

VLSI Design
Power-aware multi-core simulation for early design stage hardware/software co-optimization

Proceedings of the 21st international conference on Parallel architectures and compilation techniques
PEPON: performance-aware hierarchical power budgeting for NoC based multicores

Proceedings of the 21st international conference on Parallel architectures and compilation techniques
Power agnostic technique for efficient temperature estimation of multicore embedded systems

Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems
Review: Energy-aware performance analysis methodologies for HPC architectures-An exploratory study

Journal of Network and Computer Applications
Post-silicon power mapping techniques for integrated circuits

Integration, the VLSI Journal
Architectural implications of spatial thermal filtering

Integration, the VLSI Journal
Hardware-software coherence protocol for the coexistence of caches and local memories

SC '12 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
Improving performance per watt of asymmetric multi-core processors via online program phase classification and adaptive core morphing

ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
XEEMU: an improved xscale power simulator

PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Thermal-aware task scheduling in 3D chip multiprocessor with real-time constrained workloads

ACM Transactions on Embedded Computing Systems (TECS) - Special issue on embedded systems for interactive multimedia services (ES-IMS)
Modeling and implementation of a power estimation methodology for systemC

International Journal of Reconfigurable Computing - Special issue on Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011)
Microarchitectural design space exploration made fast

Microprocessors & Microsystems
A Study of Reusing Smartphones to Augment Elementary School Education

International Journal of Handheld Computing Research
Composable thermal modeling and simulation for architecture-level thermal designs of multicore microprocessors

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Designing energy efficient communication runtime systems: a view from PGAS models

The Journal of Supercomputing
The McPAT Framework for Multicore and Manycore Architectures: Simultaneously Modeling Power, Area, and Timing

ACM Transactions on Architecture and Code Optimization (TACO)
Local Interpolation-based Polar Format SAR: Algorithm, Hardware Implementation and Design Automation

Journal of Signal Processing Systems
Active disk meets flash: a case for intelligent SSDs

Proceedings of the 27th international ACM conference on International conference on supercomputing
Tuning the continual flow pipeline architecture

Proceedings of the 27th international ACM conference on International conference on supercomputing
Exploiting Timing Error Resilience in Processor Architecture

ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
A survey on cache tuning from a power/energy perspective

ACM Computing Surveys (CSUR)
Combating NBTI-induced aging in data caches

Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Calculating source line level energy information for Android applications

Proceedings of the 2013 International Symposium on Software Testing and Analysis
Orchestrator: a low-cost solution to reduce voltage emergencies for multi-threaded applications

Proceedings of the Conference on Design, Automation and Test in Europe
Efficient cache architectures for reliable hybrid voltage operation using EDC codes

Proceedings of the Conference on Design, Automation and Test in Europe
A fast and accurate methodology for power estimation and reduction of programmable architectures

Proceedings of the Conference on Design, Automation and Test in Europe
A power-driven thermal sensor placement algorithm for dynamic thermal management

Proceedings of the Conference on Design, Automation and Test in Europe
3D reconfigurable power switch network for demand-supply matching between multi-output power converters and many-core microprocessors

Proceedings of the Conference on Design, Automation and Test in Europe
Flicker: a dynamically adaptive architecture for power limited multicore systems

Proceedings of the 40th Annual International Symposium on Computer Architecture
GPUWattch: enabling energy optimizations in GPGPUs

Proceedings of the 40th Annual International Symposium on Computer Architecture
Criticality stacks: identifying critical threads in parallel programs using synchronization behavior

Proceedings of the 40th Annual International Symposium on Computer Architecture
Estimating mobile application energy consumption using program analysis

Proceedings of the 2013 International Conference on Software Engineering
Creation of ESL power models for communication architectures using automatic calibration

Proceedings of the 50th Annual Design Automation Conference
APPLE: adaptive performance-predictable low-energy caches for reliable hybrid voltage operation

Proceedings of the 50th Annual Design Automation Conference
A multi-agent framework for thermal aware task migration in many-core systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploiting process variability in voltage/frequency control

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An energy-efficient L2 cache architecture using way tag information under write-through policy

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecturally homogeneous power-performance heterogeneous multicore systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Employing circadian rhythms to enhance power and reliability

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Runtime power estimator calibration for high-performance microprocessors

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
S/DC: a storage and energy efficient data prefetcher

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Low power aging-aware register file design by duty cycle balancing

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
TempoMP: integrated prediction and management of temperature in heterogeneous MPSoCs

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Statistical thermal modeling and optimization considering leakage power variations

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Technical Section: Energy-aware hybrid precision selection framework for mobile GPUs

Computers and Graphics
An opportunistic prediction-based thread scheduling to maximize throughput/watt in AMPs

PACT '13 Proceedings of the 22nd international conference on Parallel architectures and compilation techniques
A unified view of non-monotonic core selection and application steering in heterogeneous chip multiprocessors

PACT '13 Proceedings of the 22nd international conference on Parallel architectures and compilation techniques
Building expressive, area-efficient coherence directories

PACT '13 Proceedings of the 22nd international conference on Parallel architectures and compilation techniques
Program-based dynamic precision selection framework with a dual-mode unified shader for mobile GPUs

Computers and Electrical Engineering
Application-aware adaptive cache architecture for power-sensitive mobile processors

ACM Transactions on Embedded Computing Systems (TECS)
An analytical approach for fast and accurate design space exploration of instruction caches

ACM Transactions on Embedded Computing Systems (TECS)
The design and implementation of heterogeneous multicore systems for energy-efficient speculative thread execution

ACM Transactions on Architecture and Code Optimization (TACO)
Dynamic microarchitectural adaptation using machine learning

ACM Transactions on Architecture and Code Optimization (TACO)
Post-compiler software optimization for reducing energy

Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
Throughput maximization for periodic real-time systems under the maximal temperature constraint

ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
Hardware support for accurate per-task energy metering in multicore systems

ACM Transactions on Architecture and Code Optimization (TACO)
Reducing instruction fetch energy in multi-issue processors

ACM Transactions on Architecture and Code Optimization (TACO)
VarEMU: an emulation testbed for variability-aware software

Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
Automated, retargetable back-annotation for host compiled performance and power modeling

Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
Real-time worst-case temperature analysis with temperature-dependent parameters

Real-Time Systems
Exascale design space exploration and co-design

Future Generation Computer Systems
The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration

Microprocessors & Microsystems
Energy-credit scheduler: An energy-aware virtual machine scheduler for cloud systems

Future Generation Computer Systems
Performance and power profiling for emulated Android systems

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design configuration selection for hard-error reliable processors via statistical rules

Microprocessors & Microsystems
Architecture exploration based on GA-PSO optimization, ANN modeling, and static scheduling

VLSI Design
Measuring GPU Power with the K20 Built-in Sensor

Proceedings of Workshop on General Purpose Processing Using GPUs
Power Modeling for Heterogeneous Processors

Proceedings of Workshop on General Purpose Processing Using GPUs
Tuning the continual flow pipeline architecture with virtual register renaming

ACM Transactions on Architecture and Code Optimization (TACO)
Power-aware code scheduling assisted with power gating and DVS

Future Generation Computer Systems

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Abstract

Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process.We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.