Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Sorting and Searching using Ternary CAMs
IEEE Micro
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Efficient Mapping of Range Classifier into Ternary-CAM
HOTI '02 Proceedings of the 10th Symposium on High Performance Interconnects HOT Interconnects
Reducing TCAM Power Consumption and Increasing Throughput
HOTI '02 Proceedings of the 10th Symposium on High Performance Interconnects HOT Interconnects
66MHz 2.3M Ternary Dynamic Content Addressable Memory
MTDT '00 Proceedings of the 2000 IEEE International Workshop on Memory Technology, Design and Testing
Packet Classification Using Extended TCAMs
ICNP '03 Proceedings of the 11th IEEE International Conference on Network Protocols
Gigabit Rate Packet Pattern-Matching Using TCAM
ICNP '04 Proceedings of the 12th IEEE International Conference on Network Protocols
EaseCAM: An Energy and Storage Efficient TCAM-Based Router Architecture for IP Lookup
IEEE Transactions on Computers
Hardware acceleration for database systems using content addressable memories
DaMoN '05 Proceedings of the 1st international workshop on Data management on new hardware
A Hybrid IP Forwarding Engine with High Performance and Low Power
ICCSA '09 Proceedings of the International Conference on Computational Science and Its Applications: Part II
Don't-care gating (DCG) TCAM design used in network routing table
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low-power TCAM design using mask-aware match-line (MAML) technique
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Virtually cool ternary content addressable memory
HotOS'13 Proceedings of the 13th USENIX conference on Hot topics in operating systems
Space and speed tradeoffs in TCAM hierarchical packet classification
Journal of Computer and System Sciences
Recursive design of hardware priority queues
Proceedings of the twenty-fifth annual ACM symposium on Parallelism in algorithms and architectures
Scalable TCAM-based regular expression matching with compressed finite automata
ANCS '13 Proceedings of the ninth ACM/IEEE symposium on Architectures for networking and communications systems
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Applications in computer networks often require high throughput access to large data structures for lookup and classification. While advanced algorithms exist to speed these search primitives on network processors and even custom application-specific integrated circuits (ASICs), achieving tight bounds on worst case performance with standard memories often requires a very careful analysis of all possible access patterns. An alternative, and often times more simple solution, is possible if a ternary CAM (TCAM) is used to perform a fully parallel search across the entire data set. Unfortunately, this parallelism means that large portions of the chip are switching during each cycle, causing large amounts of power to be consumed. While researchers at all levels of design (from algorithms to circuits) have begun to explore new ways of managing the power consumption, quantifying design alternatives is difficult due to a lack of available models. In this paper, we examine the structure of a modern TCAM and present a simple, yet accurate, power and delay model. We present techniques to estimate the dynamic power consumption and leakage power of a TCAM structure and validate the model using a combination of industrial TCAM datasheets and prior published works. Such a model is a critical first step in bridging the intellectual divide between circuit-level and algorithm-level optimizations. To demonstrate the utility of our model, we present an extensive analysis of the model by varying various architectural parameters and describe how our model can be easily extended to handle several circuit optimizations in the TCAM structure. In addition, we present a comparative study of SRAM and TCAM energy consumption to directly quantify the many design options which will be very useful for network designers to explore various power management schemes.