Computer Networks: The International Journal of Computer and Telecommunications Networking
Testing comparison faults of ternary CAMs based on comparison faults of binary CAMs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Ternary CAM power and delay model: extensions and uses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper describes a 66MHz 2.3M Content Addressable Memory (CAM) which uses DRAM technology for the basic ternary CAM cell. The chip's architecture allows a high-speed search operation and single cycle learning. The DRAM based cell structure enables implementation of a larger table size than is available in similar technology SRAM based CAMs. A new matchline sense amplifier allows fast, low power sensing of the matchline. Among the chip's many features are a DDR input interface and the ability to cascade up to eight parts without additional logic. The density and speed of this part make it suitable for many applications such as network switching.