Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Run-time power estimation in high performance microprocessors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Power prediction for intel XScale® processors using performance monitoring unit events
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
A systematic method for functional unit power estimation in microprocessors
Proceedings of the 43rd annual Design Automation Conference
Accurate and efficient regression modeling for microarchitectural performance and power prediction
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Balancing power consumption in multiprocessor systems
Proceedings of the 1st ACM SIGOPS/EuroSys European Conference on Computer Systems 2006
Identifying energy-efficient concurrency levels using machine learning
CLUSTER '07 Proceedings of the 2007 IEEE International Conference on Cluster Computing
Decomposable and responsive power models for multicore processors using performance counters
Proceedings of the 24th ACM International Conference on Supercomputing
Performance and power modeling in a multi-programmed multi-core environment
Proceedings of the 47th Design Automation Conference
SoftPower: fine-grain power estimations using performance counters
Proceedings of the 19th ACM International Symposium on High Performance Distributed Computing
A System-Level Model for Runtime Power Estimation on Mobile Devices
GREENCOM-CPSCOM '10 Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing
Understanding stencil code performance on multicore architectures
Proceedings of the 8th ACM International Conference on Computing Frontiers
Energy accounting for shared virtualized environments under DVFS using PMC-based power models
Future Generation Computer Systems
Overseer: low-level hardware monitoring and management for Java
Proceedings of the 9th International Conference on Principles and Practice of Programming in Java
Identifying the optimal energy-efficient operating points of parallel workloads
Proceedings of the International Conference on Computer-Aided Design
Pack & Cap: adaptive DVFS and thread packing under power caps
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Evaluating and modeling power consumption of multi-core processors
Proceedings of the 3rd International Conference on Future Energy Systems: Where Energy, Computing and Communication Meet
Proceedings of the 9th conference on Computing Frontiers
USENIX ATC'12 Proceedings of the 2012 USENIX conference on Annual Technical Conference
ACM Transactions on Architecture and Code Optimization (TACO)
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
DNA-inspired scheme for building the energy profile of HPC systems
E2DC'12 Proceedings of the First international conference on Energy Efficient Data Centers
Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Exploring power behaviors and trade-offs of in-situ data analytics
SC '13 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
An opportunistic prediction-based thread scheduling to maximize throughput/watt in AMPs
PACT '13 Proceedings of the 22nd international conference on Parallel architectures and compilation techniques
Leakage energy estimates for HPC applications
E2SC '13 Proceedings of the 1st International Workshop on Energy Efficient Supercomputing
Dynamic server power capping for enabling data center participation in power markets
Proceedings of the International Conference on Computer-Aided Design
Improving execution unit occupancy on SMT-based processors through hardware-aware thread scheduling
Future Generation Computer Systems
OptiPlace: Designing Cloud Management with Flexible Power Models through Constraint Programing
UCC '13 Proceedings of the 2013 IEEE/ACM 6th International Conference on Utility and Cloud Computing
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Estimating power consumption is critical for hardware and software developers, and of the latter, particularly for OS programmers writing process schedulers. However, obtaining processor and system power consumption information can be non-trivial. Simulators are time consuming and prone to error. Power meters report whole-system consumption, but cannot give per-processor or per-thread information. More intrusive hardware instrumentation is possible, but such solutions are usually employed while designing the system, and are not meant for customer use. Given these difficulties, plus the current availability of some form of performance counters on virtually all platforms (even though such counters were initially designed for system bring-up, and not intended for general programmer consumption), we analytically derive functions for real-time estimation of processor and system power consumption using performance counter data on real hardware. Our model uses data gathered from microbenchmarks that capture potential application behavior. The model is independent of our test benchmarks, and thus we expect it to be well suited for future applications. We target chip multiprocessors, analyzing effects of shared resources and temperature on power estimation, leveraging our model to implement a simple, power-aware thread scheduler. The NAS and SPEC-OMP benchmarks shows a median error of 5.8% and 3.9%, respectively. SPEC 2006 shows a marginally higher median error of 7.2%.