Accurate and efficient regression modeling for microarchitectural performance and power prediction
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
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Proceedings of the 34th annual international symposium on Computer architecture
Green Supercomputing Comes of Age
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Prediction models for multi-dimensional power-performance optimization on many cores
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Adagio: making DVS practical for complex HPC applications
Proceedings of the 23rd international conference on Supercomputing
Real time power estimation and thread scheduling via performance counters
ACM SIGARCH Computer Architecture News
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Power-aware predictive models of hybrid (MPI/OpenMP) scientific applications on multicore systems
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Virtual machine power measuring technique with bounded error in cloud environments
Journal of Network and Computer Applications
On understanding the energy consumption of ARM-based multicore servers
Proceedings of the ACM SIGMETRICS/international conference on Measurement and modeling of computer systems
Energy estimation for MPI broadcasting algorithms in large scale HPC systems
Proceedings of the 20th European MPI Users' Group Meeting
Modeling energy consumption for master---slave applications
The Journal of Supercomputing
Improving execution unit occupancy on SMT-based processors through hardware-aware thread scheduling
Future Generation Computer Systems
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We present and evaluate a surrogate model, based on hardware performance counter measurements, to estimate computer system power consumption. Power and energy are especially important in the design and operation of large data centers and of clusters used for scientific computing. Tradeoffs are made between performance and power consumption, this needs to be dynamic because activity varies over time. While it is possible to instrument systems for fine-grain power monitoring, such instrumentation is costly and not commonly available. Furthermore, the latency and sampling periods of hardware power monitors can be large compared to time scales at which workloads can change and dynamic power controls can operate. Given these limitations, we argue that surrogate models of the kind we present here can provide low-cost and accurate estimates of power consumption to drive on-line dynamic control mechanisms and for use in off-line tuning. In this brief paper, we discuss a general approach to building system power estimation models based on hardware performance counters. Using this technique, we then present a model for an Intel Core i7 system that has an absolute estimation error of 5.32 percent (median) and acceptable data collection overheads on varying workloads, CPU power states (frequency and voltage), and number of active cores. Since this method is based on event sampling of hardware counters, one can make a tradeoff between estimation accuracy and data-collection overhead.