Power analysis of embedded software: a first step towards software power minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
A low power unified cache architecture providing power and performance flexibility (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Supercomputing '96 Proceedings of the 1996 ACM/IEEE conference on Supercomputing
PASTE '01 Proceedings of the 2001 ACM SIGPLAN-SIGSOFT workshop on Program analysis for software tools and engineering
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
A Portable Programming Interface for Performance Evaluation on Modern Processors
International Journal of High Performance Computing Applications
Controlling leakage power with the replacement policy in slumberous caches
Proceedings of the 2nd conference on Computing frontiers
Real time power estimation and thread scheduling via performance counters
ACM SIGARCH Computer Architecture News
PowerPack: Energy Profiling and Analysis of High-Performance Systems and Applications
IEEE Transactions on Parallel and Distributed Systems
CMOS VLSI Design: A Circuits and Systems Perspective
CMOS VLSI Design: A Circuits and Systems Perspective
Portable, scalable, per-core power estimation for intelligent resource management
GREENCOMP '10 Proceedings of the International Conference on Green Computing
Toward Dark Silicon in Servers
IEEE Micro
Complete System Power Estimation Using Processor Performance Events
IEEE Transactions on Computers
Measuring Energy and Power with PAPI
ICPPW '12 Proceedings of the 2012 41st International Conference on Parallel Processing Workshops
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Large-scale high-performance systems are energy constrained. With thousands of processing cores at their disposal, these machines contain large amounts of on-chip caches. With a trend of decreasing thresholds in transistors, the amount of leakage current and energy losses has increased dramatically. Coupling the two trends, on-chip caches are responsible for a large portion of total leakage energy losses. In this work, we quantify the on-chip leakage energy losses across a wide set of applications. Our scheme profiles applications to measure cache accesses in order to estimate energy consumption across various levels of caches. Our study indicates that the leakage energy is the dominant form of energy dissipation in on-chip caches and may account for up to 80% of total cache energy, and this trend is expected to increase with every new generation of semiconductor process. Our results also suggest that compiler optimizations have a very limited effect on the total energy consumption of the caches and irrespective of the compiler optimizations, the problem of leakage in caches cannot be effectively addressed by software techniques but requires intervention at circuit and architectural levels. The problem of leakage in caches cannot be neglected in attacking the energy barrier to building exascale systems.