Benchmark Synthesis Using the LRU Cache Hit Function
IEEE Transactions on Computers
ICS '99 Proceedings of the 13th international conference on Supercomputing
Bounds modelling and compiler optimizations for superscalar performance tuning
Journal of Systems Architecture: the EUROMICRO Journal - Special double issue on microprocessor architecture
Dhrystone: a synthetic systems programming benchmark
Communications of the ACM
The benefits of event: driven energy accounting in power-sensitive systems
EW 9 Proceedings of the 9th workshop on ACM SIGOPS European workshop: beyond the PC: new challenges for the operating system
Run-time modeling and estimation of operating system power consumption
SIGMETRICS '03 Proceedings of the 2003 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Instruction Level Power Analysis and Optimization of Software
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Microbenchmarks for determining branch predictor organization
Software—Practice & Experience - Research Articles
Improved automatic testcase synthesis for performance model validation
Proceedings of the 19th annual international conference on Supercomputing
A systematic method for functional unit power estimation in microprocessors
Proceedings of the 43rd annual Design Automation Conference
SPEC CPU2006 benchmark descriptions
ACM SIGARCH Computer Architecture News
Accurate on-line prediction of processor and memoryenergy usage under voltage scaling
EMSOFT '07 Proceedings of the 7th ACM & IEEE international conference on Embedded software
Distilling the essence of proprietary workloads into miniature benchmarks
ACM Transactions on Architecture and Code Optimization (TACO)
Real time power estimation and thread scheduling via performance counters
ACM SIGARCH Computer Architecture News
Decomposable and responsive power models for multicore processors using performance counters
Proceedings of the 24th ACM International Conference on Supercomputing
Power and thermal characterization of POWER6 system
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Portable, scalable, per-core power estimation for intelligent resource management
GREENCOMP '10 Proceedings of the International Conference on Green Computing
Benchmark synthesis for architecture and compiler exploration
IISWC '10 Proceedings of the IEEE International Symposium on Workload Characterization (IISWC'10)
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
SWEEP: evaluating computer system energy efficiency using synthetic workloads
Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers
Automated Full-System Power Characterization
IEEE Micro
IBM POWER7 multicore server processor
IBM Journal of Research and Development
Adaptive energy-management features of the IBM POWER 7 chip
IBM Journal of Research and Development
Automated di/dt stressmark generation for microprocessor power delivery networks
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis
WEST: Cloning data cache behavior using Stochastic Traces
HPCA '12 Proceedings of the 2012 IEEE 18th International Symposium on High-Performance Computer Architecture
Complete System Power Estimation Using Processor Performance Events
IEEE Transactions on Computers
POTRA: a framework for building power models for next generation multicore architectures
Proceedings of the 12th ACM SIGMETRICS/PERFORMANCE joint international conference on Measurement and Modeling of Computer Systems
Microprocessor power estimation using profile-driven program synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Counter-Based Power Modeling Methods
The Computer Journal
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Microprocessor-based systems today are composed of multi-core, multi-threaded processors with complex cache hierarchies and gigabytes of main memory. Accurate characterization of such a system, through predictive pre-silicon modeling and/or diagnostic post silicon measurement based analysis are increasingly cumbersome and error prone. This is especially true of energy-related characterization studies. In this paper, we take the position that automated micro-benchmarks generated with particular objectives in mind hold the key to obtaining accurate energy-related characterization. As such, we first present a flexible micro-benchmark generation framework (MicroProbe) that is used to probe complex multi-core/multithreaded systems with a variety and range of energy-related queries in mind. We then present experimental results centered around an IBM POWER7 CMP/SMT system to demonstrate how the systematically generated micro-benchmarks can be used to answer three specific queries: (a) How to project application-specific (and if needed, phase-specific) power consumption with component-wise breakdowns? (b) How to measure energy-per-instruction (EPI) values for the target machine? (c) How to bound the worst-case (maximum) power consumption in order to determine safe, but practical (i.e. affordable) packaging or cooling solutions? The solution approaches to the above problems are all new. Hardware measurement based analysis shows superior power projection accuracy (with error margins of less than 2.3% across SPEC CPU2006) as well as maxpower stressing capability (with 10.7% increase in processor power over the very worst-case power seen during the execution of SPEC CPU2006 applications).