The PowerPC performance modeling methodology
Communications of the ACM
Value locality and load value prediction
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Trace cache: a low latency approach to high bandwidth instruction fetching
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
The PowerPC 604 RISC microprocessor
IEEE Micro
Can Trace-Driven Simulators Accurately Predict Superscalar Performance?
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Testing for Function and Performance: Towards anIntegrated Processor Validation Methodology
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
A Buffer-Oriented Methodology for Microarchitecture Validation
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Measuring experimental error in microprocessor simulation
SSR '01 Proceedings of the 2001 symposium on Software reusability: putting software reuse in context
Measuring Experimental Error in Microprocessor Simulation
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
A Model of a Microprocessor with a Wide Command Word
Cybernetics and Systems Analysis
Mispredicted Path Cache Effects
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
A Statistically Rigorous Approach for Improving Simulation Methodology
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
IBM Journal of Research and Development
Journal of Systems and Software - Special issue: Performance modeling and analysis of computer systems and networks
Toward an Evaluation Infrastructure for Power and Energy Optimizations
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 11 - Volume 12
Improved automatic testcase synthesis for performance model validation
Proceedings of the 19th annual international conference on Supercomputing
Improving Computer Architecture Simulation Methodology by Adding Statistical Rigor
IEEE Transactions on Computers
Evaluating the impact of the simulation environment on experimentation results
Performance Evaluation
Simulation of Computer Architectures: Simulators, Benchmarks, Methodologies, and Recommendations
IEEE Transactions on Computers
The design and utility of the ML-RSIM system simulator
Journal of Systems Architecture: the EUROMICRO Journal
Speed versus Accuracy Trade-Offs in Microarchitectural Simulations
IEEE Transactions on Computers
Calibration of abstract performance models for system-level design space exploration
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
A novel SoC platform based multi-IP verification and performance measurement
International Journal of Information and Communication Technology
Generation and calibration of compositional performance analysis models for multi-processor systems
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Automatic performance model synthesis from hardware verification models
Proceedings of the 2nd ACM/SPEC International Conference on Performance engineering
An accurate architectural simulator for ARM1136
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
ACM Transactions on Embedded Computing Systems (TECS)
A full lifecycle performance verification methodology for multicore systems-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
| Hi-index | 4.11 |
The microprocessor industry can capably predict the clock frequency and functionality of first siliconýthe first small set of chips made for a new design. However, predicting first silicon's performance on real programs remains a challenge. Microprocessor designers use performance models to evaluate how new ideas affect performance. However, it is very difficult to know if these models are accurate. The problem lies in understanding the true performance effect of a new feature. In an unstable performance model, model changes may inadvertently remove existing bugs, introduce new bugs, or reduce the performance impact of an existing bug. This effect can mislead designers into implementing features that do not actually improve performance or not implementing features that would. This article presents experimental results on calibrating a performance model against actual hardware, and on the basis of these results, suggests a systematic method for validating performance models. These results highlight the difficulty in developing an accurate performance model. As microarchitecture complexity continues to increase, especially with the incorporation of aggressive speculation techniques, accurate performance modeling and the validation of performance models will continue to be a great challenge.