Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Instruction level profiling and evaluation of the IBM/6000
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Performance evaluation of the PowerPC 620 microarchitecture
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
EXPLORER: a retargetable and visualization-based trace-driven simulator for superscalar processors
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
The PowerPC 620 microprocessor: a high performance superscalar RISC microprocessor
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
Systematic Validation of Pipeline Interlock for Superscalar Microarchitectures
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
A visualization-based microarchitecture workbench
A visualization-based microarchitecture workbench
Value locality and load value prediction
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Exceeding the dataflow limit via value prediction
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Retargetable cache simulation using high level processor models
ACSAC '01 Proceedings of the 6th Australasian conference on Computer systems architecture
Exploiting Value Locality to Exceed the Dataflow Limit
International Journal of Parallel Programming
Visualizing Application Behavior on Superscalar Processors
INFOVIS '99 Proceedings of the 1999 IEEE Symposium on Information Visualization
OCCN: a NoC modeling framework for design exploration
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
| Hi-index | 4.10 |
Single-chip microprocessors are achieving phenomenal performance due to advances being made in several enabling technologies. But this performance increase is accompanied by increasing processor complexity. The design of complex superscalar processors requires using sophisticated software tools, most notably simulators. Most existing simulators, however, suffer from three weaknesses. They lack retargetability, visualization support, and interactive control. This article describes the Visualization-Based Microarchitecture Workbench (VMW), which addresses these weaknesses. VMW enables a processor architect to efficiently and effectively explore the machine design space. A designer can use VMW to rigorously specify a new microarchitecture, automatically generate a performance simulator for the machine, and quickly assess machine performance. Performance data are machine-cycle accurate and can be viewed using a rich set of visualization instruments provided by VMW. Simulators for the DEC Alpha AXP 21064 and 21164, the IBM RS/6000, and the PowerPC 601and 620 microprocessors (and modifications and extensions of these machines) have been generated and executed. VMW has been demonstrated at a number of industrial sites, and its public domain distribution is planned.