Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Automatic test program generation for pipelined processors
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
The Stanford FLASH multiprocessor
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Formally verifying a microprocessor using a simulation methodology
DAC '94 Proceedings of the 31st annual Design Automation Conference
Performance evaluation of the PowerPC 620 microarchitecture
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Verification of a Pipelined Microprocessor Using Clio
Workshop on Hardware Specification, Verification and Synthesis: Mathematical Aspects
The PowerPC 620 microprocessor: a high performance superscalar RISC microprocessor
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
A visualization-based microarchitecture workbench
A visualization-based microarchitecture workbench
Micro architecture coverage directed generation of test programs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Cost Evaluation of Coverage Directed Test Generation for the IBM Mainframe
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A framework for systematic validation and debugging of pipeline simulators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Generating test programs to cover pipeline interactions
Proceedings of the 46th Annual Design Automation Conference
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Abstract: The paper presents a new approach to microarchitecture validation that adopts a paradigm analogous to that of automatic test pattern generation (ATPG) for digital logic testing. In this approach, the microarchitecture is rigorously specified in a set of machine description files. Based on these files, all possible pipeline hazards can be systematically identified Using this hazard list (analogous to a fault list for ATPG), specific sequences of instructions (analogous to test patterns) are automatically generated and constitute the test program. The execution of this test program validates the correct detection and resolution of all interinstruction dependences by the microarchitecture's pipeline interlock mechanism. Actual software tools have been developed for the automatic construction of the hazard list and the automatic generation of the test sequences. These explicitly generated can achieve higher sequences coverage in fewer cycles than adhoc approaches. 100% coverage of the hazard list can be ensured. These tools have been applied to four contemporary superscalar processors, namely the Alpha AXP 21064 and 21164 microprocessors, and the PowerPC 601 and 620 microprocessors.