Automatic functional test generation using the extended finite state machine model
DAC '93 Proceedings of the 30th international Design Automation Conference
Test program generation for functional verification of PowerPC processors in IBM
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Micro architecture coverage directed generation of test programs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Coverage-Directed Test Generation Using Symbolic Techniques
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Systematic Validation of Pipeline Interlock for Superscalar Microarchitectures
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Interactive presentation: Functional and timing validation of partially bypassed processor pipelines
Proceedings of the conference on Design, automation and test in Europe
Specification-driven directed test generation for validation of pipelined processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Functional test generation using design and property decomposition techniques
ACM Transactions on Embedded Computing Systems (TECS)
Extensible environment for test program generation for microprocessors
Programming and Computing Software
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Functional validation of a processor design through execution of a suite of test programs is common industrial practice. In this paper, we develop a high-level architectural specification driven methodology for systematic test-suite generation. Our primary contribution is an automated test-suite generation methodology that covers all possible processor pipeline interactions. To accomplish this automation, we (1) develop a fully formal processor model based on communicating extended finite state machines, and (2) traverse the processor model for on-the-fly generation of short test programs covering all reachable states and transitions. Our test generation method achieves several orders of magnitude reduction in test-suite size compared to the previously proposed formal approaches for test generation, leading to drastic reduction in validation effort.