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ISDL: an instruction set description language for retargetability
DAC '97 Proceedings of the 34th annual Design Automation Conference
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MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
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DATE '99 Proceedings of the conference on Design, automation and test in Europe
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Proceedings of the 36th annual ACM/IEEE Design Automation Conference
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CASES '00 Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Asim: A Performance Model Framework
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EDTC '95 Proceedings of the 1995 European conference on Design and Test
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DAC '79 Proceedings of the 16th Design Automation Conference
Automatic Generation of Microarchitecture Simulators
ICCL '98 Proceedings of the 1998 International Conference on Computer Languages
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Customisable EPIC Processor: Architecture and Tools
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Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
C Compiler Retargeting Based on Instruction Semantics Models
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Hybrid simulation for embedded software energy estimation
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Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable design
Proceedings of the 42nd annual Design Automation Conference
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Proceedings of the conference on Design, automation and test in Europe: Proceedings
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MEDEA '05 Proceedings of the 2005 workshop on MEmory performance: DEaling with Applications , systems and architecture
Fast cycle-approximate instruction set simulation
SCOPES '08 Proceedings of the 11th international workshop on Software & compilers for embedded systems
Signature-Based Calibration of Analytical System-Level Performance Models
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Processor Description Languages
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
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CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
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Proceedings of the 46th Annual Design Automation Conference
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Quasi-static voltage scaling for energy minimization with time constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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ACM Transactions on Embedded Computing Systems (TECS)
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Proceedings of the 50th Annual Design Automation Conference
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Given the growth in application-specific processors, there is a strong need for a retargetable modeling framework that is capable of accurately capturing complex processor behaviors and generating efficient simulators. We propose the operation state machine (OSM) computation model to serve as the foundation of such a modeling framework. The OSM model separates the processor into two interacting layers: the operation layer where operation semantics and timing are modeled, and the hardware layer where disciplined hardware units interact. This declarative model allows for direct synthesis of micro-architecture simulators as it encapsulates precise concurrency semantics of microprocessors. We illustrate the practical benefits of this model through two case studies 驴 the StrongARM core and the PowerPC-750 superscalar processor. The experimental results demonstrate that the OSM model has excellent modeling productivity and model efficiency. Additional applications of this modeling framework include derivation of information required by compilers and formal analysis for processor validation.