Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
The microprogramming of pipelined processors
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Architecture Implementation Using the Machine Description Language LISA
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Flow control and micro-architectural mechanisms for extending the performance of interconnection networks
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Object-oriented modeling and synthesis of SystemC specifications
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Teaching Computer Organization with HDLs: An Incremental Approach
MSE '05 Proceedings of the 2005 IEEE International Conference on Microelectronic Systems Education
SystemC transaction level models and RTL verification
Proceedings of the 43rd annual Design Automation Conference
Transaction Based Modeling and Verification of Hardware Protocols
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Automating Hazard Checking in Transaction-Level Microarchitecture Models
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Verification Driven Formal Architecture and Microarchitecture Modeling
MEMOCODE '07 Proceedings of the 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign
Scoot: a tool for the analysis of SystemC models
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
Operation-centric hardware description and synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Specification and encoding of transaction interaction properties
Formal Methods in System Design
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Current RTL-based design methodologies face significant scaling challenges related to the difficulty of designing, modifying, and verifying RTL. RTL contains primarily low level structural information about the design. In contrast, the microarchitecture-level is much closer to the specification level, making it an effective entry point for hardware design. The explicit description of the high-level units of work is also beneficial for verification. Currently used models for high level design have very complex semantics. In this paper, we present a microarchitectural modeling language with simpler semantics. We demonstrate that it results in a significantly simpler synthesis to Verilog, providing for integration with existing RTL flows. Moreover, the simple semantics of the model enable the generation of PSL assertions for functionally verifying correctness of the synthesis. We demonstrate the efficacy of this approach through two case-studies---a router switch and a processor design. We synthesized both designs, and formally verified the synthesis using the generated assertions.