Limits for automatic verification of finite-state concurrent systems
Information Processing Letters
Reasoning about networks with many identical finite-state processes
PODC '86 Proceedings of the fifth annual ACM symposium on Principles of distributed computing
Model checking
Parameterized Verification of Multithreaded Software Libraries
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Verification of Infinite State Systems by Compositional Model Checking
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Automatic Verification of Parameterized Synchronous Systems (Extended Abstract)
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Symbolic Model Checking of Infinite State Systems Using Presburger Arithmetic
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Reducing Model Checking of the Many to the Few
CADE-17 Proceedings of the 17th International Conference on Automated Deduction
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
SystemC transaction level models and RTL verification
Proceedings of the 43rd annual Design Automation Conference
Interprocedural analysis of asynchronous programs
Proceedings of the 34th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Transaction Based Modeling and Verification of Hardware Protocols
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Automating Hazard Checking in Transaction-Level Microarchitecture Models
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Verification Driven Formal Architecture and Microarchitecture Modeling
MEMOCODE '07 Proceedings of the 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign
Supporting RTL flow compatibility in a microarchitecture-level design framework
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
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Transaction-level modeling is used in hardware design for describing designs at a higher level compared to the register-transfer level (RTL) (e.g. Cai and Gajski in CODES+ISSS '03: proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pp. 19---24, 2003; Chen et al. in FMCAD '07: proceedings of the formal methods in computer aided design, pp. 53---61, 2007; Mahajan et al. in MEMOCODE '07: proceedings of the 5th IEEE/ACM international conference on formal methods and models for codesign, pp. 123---132, 2007; Swan in DAC '06: proceedings of the 43rd annual conference on design automation, pp. 90---92, 2006). Each transaction represents a unit of work, which is also a useful unit for design verification. In such models, there are many properties of interest which involve interactions between multiple transactions. Examples of this are ordering relationships in sequential processing and hazard checking in pipelined circuits. Writing such properties on the RTL design requires significant expertise in understanding the higher-level computation being done in a given RTL design and possible instrumentation of the RTL to express the property of interest. This is a barrier to the easy use of such properties in RTL designs.In this paper, we consider specification of interaction properties at the transaction-level and the subsequent encoding of the property and the transaction-level model as a finite-state system for model checking. We discuss how the encoded finite-state system can be automatically generated from the specification of the property and the transaction-level model, and illustrate this through simple examples.