Surviving the SOC revolution: a guide to platform-based design
Surviving the SOC revolution: a guide to platform-based design
System Design with SystemC
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Partial order reduction for scalable testing of systemC TLM designs
Proceedings of the 45th annual Design Automation Conference
Supporting RTL flow compatibility in a microarchitecture-level design framework
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Specification and encoding of transaction interaction properties
Formal Methods in System Design
A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulation
Proceedings of the 49th Annual Design Automation Conference
A systematic approach to configurable functional verification of HW IP blocks at transaction level
Computers and Electrical Engineering
Model driven resource usage simulation for critical embedded systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are being reused for RTL verification. The paper discusses how the task of system verification is changing as systems become more complex and it discusses how companies are striving to eliminate fragmentation within their design and verification flows by leveraging SystemC transaction level models.