SystemC transaction level models and RTL verification
Proceedings of the 43rd annual Design Automation Conference
Validate, simulate, and implement ARINC653 systems using the AADL
Proceedings of the ACM SIGAda annual international conference on Ada and related technologies
| Hi-index | 0.00 |
Facing a growing complexity, embedded systems design relies on model-based approaches to ease the exploration of a design space. A key aspect of such exploration is performance evaluation, mainly depending on usage of the hardware resources. In model-driven engineering, hardware resources usage is often approximated by static properties. In this paper, we propose an extensible modeling framework, to describe with different levels of detail the hardware resource usage. Our method relies on the AADL to describe the whole system, and SystemC to refine the execution platform description. In this paper we expose how we generate and compose SystemC models from the execution platform model described in AADL. We also present promising experimental results obtained on an avionics use-case.