An IP-based on-chip packet-switched network
Networks on chip
FIFO power optimization for on-chip networks
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Low-Latency Virtual-Channel Routers for On-Chip Networks
Proceedings of the 31st annual international symposium on Computer architecture
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
Proceedings of the 32nd annual international symposium on Computer Architecture
Communication latency aware low power NoC synthesis
Proceedings of the 43rd annual Design Automation Conference
Architecting a reliable CMP switch architecture
ACM Transactions on Architecture and Code Optimization (TACO)
A theory of mutations with applications to vacuity, coverage, and fault tolerance
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Supporting RTL flow compatibility in a microarchitecture-level design framework
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Scalable specification mining for verification and diagnosis
Proceedings of the 47th Design Automation Conference
Design as you see FIT: system-level soft error analysis of sequential circuits
Proceedings of the Conference on Design, Automation and Test in Europe
A practical low-latency router architecture with wing channel for on-chip network
Microprocessors & Microsystems
Abstraction-based performance verification of NoCs
Proceedings of the 48th Design Automation Conference
Network on chip for parallel DSP architectures
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Explicit modeling of control and data for improved NoC router estimation
Proceedings of the 49th Annual Design Automation Conference
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