Network on chip for parallel DSP architectures

Authors:
Yuanli Jing;Xiaoya Fan;Deyuan Gao;Jian Hu
Affiliations:
Aviation Microelectronic Center, Northwestern Polytechnical University, Xi’an, China;Aviation Microelectronic Center, Northwestern Polytechnical University, Xi’an, China;Aviation Microelectronic Center, Northwestern Polytechnical University, Xi’an, China;Aviation Microelectronic Center, Northwestern Polytechnical University, Xi’an, China
Venue:
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Year:
2005

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Abstract

Network-on-Chip is a new methodology of System-on-Chip design. It can be used to improve communication performance among many computing nodes of parallel DSP architectures. Simulations based on the 16-node 2D-mesh DragonFly DSP architecture show that the routing distance of 72.9% inter-node communication is 1. A fast local router is proposed to improve the performance of this communication. Experiments on our simulator show that overall inter-node communication delay is decreased by 59.4%.