SPLASH: Stanford parallel applications for shared-memory
ACM SIGARCH Computer Architecture News
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Evaluating virtual channels for cache-coherent shared-memory multiprocessors
ICS '96 Proceedings of the 10th international conference on Supercomputing
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Parallel Computer Architecture: A Hardware/Software Approach
Parallel Computer Architecture: A Hardware/Software Approach
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
The Alpha 21364 Network Architecture
IEEE Micro
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Power constrained design of multiprocessor interconnection networks
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Networks on Chip: A New Paradigm for Systems on Chip Design
Proceedings of the conference on Design, automation and test in Europe
Flow control and micro-architectural mechanisms for extending the performance of interconnection networks
Power-driven Design of Router Microarchitectures in On-chip Networks
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Packetized On-Chip Interconnect Communication Analysis for MPSoC
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Low-power system-level design of VLSI packet switching fabrics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As the design community moves towards architecting multiprocessor systems-on-chip (MPSoC), it is widely believed that an on-chip interconnection network is potentially the best candidate to satisfy the high aggregate throughput needed by dozens of IP blocks. In this context, power (energy) estimation and reduction techniques for switches and links, the core components of an interconnection network, gain added significance. FIFO buffers are a key component of a majority of network switches - buffers have been estimated to be the single largest power consumer for a typical switch in an on-chip network. In this report, we analyze energy-power characteristics of FIFOs for on-chip networks and propose an optimization to reduce FIFO energy consumption in the context of an on-chip network. Our experimental results demonstrate promising reductions in energy consumptions (19-33% for 256 and 512 bit wide links). Furthermore, our approach yields increasing energy reduction for wider links that are very likely to be used in future on-chip networks.