Computer organization and design (2nd ed.): the hardware/software interface
Computer organization and design (2nd ed.): the hardware/software interface
Memory exploration for low power, embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
Parallel Computer Architecture: A Hardware/Software Approach
Parallel Computer Architecture: A Hardware/Software Approach
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Power constrained design of multiprocessor interconnection networks
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Networks on Chip: A New Paradigm for Systems on Chip Design
Proceedings of the conference on Design, automation and test in Europe
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
A complexity theory for VLSI
Low-power system-level design of VLSI packet switching fabrics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Network-on-Chip Modeling for System-Level Multiprocessor Simulation
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Distributed Multimedia System Design: A Holistic Perspective
Proceedings of the conference on Design, automation and test in Europe - Volume 2
System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
FIFO power optimization for on-chip networks
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Plug-in of power models in the StepNP exploration platform: analysis of power/performance trade-offs
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Design and analysis of an NoC architecture from performance, reliability and energy perspective
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
Area and performance optimization of a generic network-on-chip architecture
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Achieving structural and composable modeling of complex systems
International Journal of Parallel Programming - Special issue: The next generation software program
On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Arbiter synthesis approach for SoC multi-processor systems
Computers and Electrical Engineering
A system-level design methodology for application-specific networks-on-chip
Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
Throughput-oriented NoC topology generation and analysis for high performance SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A parallel genetic algorithm on a multi-processor system-on-chip
IEA/AIE'10 Proceedings of the 23rd international conference on Industrial engineering and other applications of applied intelligent systems - Volume Part II
A middleware approach to achieving fault tolerance of Kahn process networks on networks on chips
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
MpAssign: A Framework for Solving the Many-Core Platform Mapping Problem
Software—Practice & Experience
System-level application-specific NoC design for network and multimedia applications
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Energy-aware task mapping and scheduling for reliable embedded computing systems
ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
Communication and migration energy aware task mapping for reliable multiprocessor systems
Future Generation Computer Systems
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Interconnect networks play a critical role in shared memory multi-processor systems-on-chip (MPSoC) designs. MPSoC performance and power consumption are greatly affected by the packet dataflows that are transported on the network. In this paper, by introducing a packetized on-chip communication power model, we discuss the packetization impact on MPSoC performance and power consumption. Particularly, we propose a quantitative analysis method to evaluate the relationship between different design options (cache, memory, packetization scheme, etc.) at the architectural level. From the benchmark experiments, we show that optimal performance and power tradeoff can be achieved by the selection of appropriate packet sizes.