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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The increasing complexity of Multi-Processor System on Chip (MPSoC) is requiring communication infrastructures that will efficiently accommodate the communication needs of the integrated computation resources. Exploring the arbitration space is crucial for achieving low latency communication. This paper illustrates an arbiter synthesis approach that allows a high performance MPSoC communication for multi-bus and Network on Chip (NoC) architectures. A cost function has been formulated in order to affect the priority order to each component or each set of components in a manner that minimizes the communication latency and generates a multi-level arbiter. The performance of the proposed approach have been analyzed in a design of an 8x8 ATM switch subsystem and a MPEG4 decoder mapped onto a 2-D mesh NoC. The results demonstrate that the MPSoC arbiter is well suited to provide high priority communication traffic with low latencies by allowing a preemption of lower priority transport. The sum of the mean waiting time at the eight ports of the ATM switch is minimum under the MPSoC arbitration scheme (4.30 cycle per word) while it is 3.00 times larger under the poorer performance arbitration scheme. In the case of the MPEG4 decoder, the average packet latency of the MPSoC is about 480 cycles while it is 640 cycles in the poorer performance arbitration scheme under a 0.4 flits/cycle injection rate.