SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An Application-Specific Design Methodology for STbus Crossbar Generation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Quality-of-service and error control techniques for mesh-based network-on-chip architectures
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Key research problems in NoC design: a holistic perspective
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Mapping and configuration methods for multi-use-case networks on chips
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
SAGA: synthesis technique for guaranteed throughput NoC architectures
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Application-specific network-on-chip architecture customization via long-range link insertion
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A methodology for mapping multiple use-cases onto networks on chips
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A low complexity heuristic for design of custom network-on-chip architectures
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Application specific NoC design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the conference on Design, automation and test in Europe: Proceedings
System level design paradigms: Platform-based design and communication synthesis
Proceedings of the 41st annual Design Automation Conference
Computation and communication refinement for multiprocessor SoC design: A system-level perspective
Proceedings of the 41st annual Design Automation Conference
Linear-programming-based techniques for synthesis of network-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-level power-performance trade-offs in bus matrix communication architecture synthesis
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
NoC Design and Implementation in 65nm Technology
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip
Proceedings of the conference on Design, automation and test in Europe
Analysis and optimization of prediction-based flow control in networks-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Micro
Arbiter synthesis approach for SoC multi-processor systems
Computers and Electrical Engineering
NoCOUT: NoC topology generation with mixed packet-switched and point-to-point networks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Invited paper: Network-on-Chip design and synthesis outlook
Integration, the VLSI Journal
Synthesis of networks on chips for 3D systems on chips
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Synthesis of predictable networks-on-chip-based interconnect architectures for chip multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automated technique for design of NoC with minimal communication latency
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
NoC topology synthesis for supporting shutdown of voltage islands in SoCs
Proceedings of the 46th Annual Design Automation Conference
Custom networks-on-chip architectures with multicast routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Yield enhancement by robust application-specific mapping on Network-on-Chips
Proceedings of the 2nd International Workshop on Network on Chip Architectures
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Quality-of-service and error control techniques for mesh-based network-on-chip architectures
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
IEEE Transactions on Circuits and Systems II: Express Briefs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Networks on Chips: from research to products
Proceedings of the 47th Design Automation Conference
Proceedings of the 47th Design Automation Conference
A method to remove deadlocks in networks-on-chips with wormhole flow control
Proceedings of the Conference on Design, Automation and Test in Europe
SunFloor 3D: a tool for networks on chip topology synthesis for 3D systems on chips
Proceedings of the Conference on Design, Automation and Test in Europe
Synthesis of low-overhead configurable source routing tables for network interfaces
Proceedings of the Conference on Design, Automation and Test in Europe
Sunfloor 3D: a tool for networks on chip topology synthesis for 3-D systems on chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
"It's a small world after all": noc performance optimization via long-range link insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of network-on-chip architectures with a genetic algorithm-based technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A tree-based topology synthesis for on-chip network
Proceedings of the International Conference on Computer-Aided Design
System-level application-specific NoC design for network and multimedia applications
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Designing best effort networks-on-chip to meet hard latency constraints
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures
CusNoC: fast full-chip custom NoC generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Application-Specific Network-on-Chip synthesis with flexible router Placement
Journal of Systems Architecture: the EUROMICRO Journal
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We propose an efficient heuristic for the constraint-drivencommunication synthesis (CDCS) of on-chip communication networks.The complexity of the synthesis problems comes from the number ofconstraints that have to be considered. In this paper we propose tocluster constraints to reduce the number that needs to beconsidered by the optimization algorithm. Then a quadraticprogramming approach is used to solve the communication synthesisproblem with the clustered constraints. We provide an analyticalmodel that justifies our choice of the clustering cost function andwe discuss a set of experiments showing the effectiveness of theoverall approach with respect to the exact algorithm.