Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Efficient Synthesis of Networks On Chip
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A unified approach to constrained mapping and routing on network-on-chip architectures
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Application-specific network-on-chip architecture customization via long-range link insertion
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Application specific NoC design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Linear-programming-based techniques for synthesis of network-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
NoCOUT: NoC topology generation with mixed packet-switched and point-to-point networks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
UNISM: unified scheduling and mapping for general networks on chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Many embedded SoC architectures require minimal on-chip communication latency and jitter. Further, each communication transaction is expected to display some jitter in its start time due to dynamic events. The paper presents a novel synthesis technique that generates an optimized NoC architecture composed of best effort traffic class routers. The technique minimizes both the average packet latency and jitter in the presence of transaction initiation jitter. In comparison to an existing approach the designs generated by our technique demonstrated 41% reduction in average latency, 39% reduction in standard deviation of latency, identical power consumption and 24% increase in router resources.