Performance Analysis of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
A comprehensive analytical model for wormhole routing in multicomputer systems
Journal of Parallel and Distributed Computing
The design and use of simplepower: a cycle-accurate energy estimation tool
Proceedings of the 37th Annual Design Automation Conference
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Toward achieving energy efficiency in presence of deep submicron noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
Micronetwork-based integration for SOCs: 673
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
An adaptive low-power transmission scheme for on-chip networks
Proceedings of the 15th international symposium on System Synthesis
A bus energy model for deep submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Leakage power modeling and optimization in interconnection networks
Proceedings of the 2003 international symposium on Low power electronics and design
Managing Power Consumption in Networks on Chip
Proceedings of the conference on Design, automation and test in Europe
Low Power Error Resilient Encoding for On-Chip Data Buses
Proceedings of the conference on Design, automation and test in Europe
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Efficient Synthesis of Networks On Chip
ICCD '03 Proceedings of the 21st International Conference on Computer Design
xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs
ICCD '03 Proceedings of the 21st International Conference on Computer Design
The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A Power and Performance Model for Network-on-Chip Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Error Control Coding, Second Edition
Error Control Coding, Second Edition
Adapative Error Protection for Energy Efficiency
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Micro-Network for SoC: Implementation of a 32-Port SPIN network
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Cost considerations in network on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
VHDL-based simulation environment for Proteo NoC
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Instruction-based system-level power evaluation of system-on-a-chip peripheral cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A global wiring paradigm for deep submicron design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power system-level design of VLSI packet switching fabrics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Traffic generation and performance evaluation for mesh-based NoCs
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
HIBI Communication Network for System-on-Chip
Journal of VLSI Signal Processing Systems
Linear-programming-based techniques for synthesis of network-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Area and performance optimization of a generic network-on-chip architecture
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Run-time adaptive on-chip communication scheme
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions
Journal of Systems Architecture: the EUROMICRO Journal
Minimizing virtual channel buffer for routers in on-chip communication architectures
Proceedings of the conference on Design, automation and test in Europe
A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect
Fundamenta Informaticae - Application of Concurrency to System Design
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Network-on-a-chip (NoC) has been proposed as a solution for addressing the design challenges of future high-performance system-on-chip architectures in the nanoscale regime. Many real-time applications require input data that arrives with low delay jitter. Such communication traffic can only be supported by incorporating multiple levels of service in the interconnection network. Further, as technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, and radiation induced effects, that are likely to reduce the reliability of data. Hence, effective error control schemes are required for ensuring data integrity. This paper addresses two important aspects of NoC architectures, quality of service and error control schemes and makes the following contributions: (i) it presents techniques for supporting guaranteed throughput (for low delay jitter traffic) and best-effort traffic quality levels in NoC router, (ii) it presents architectures for integrating error control schemes in the NoC router architecture, and (iii) it presents cycle accurate power and performance models of the two architecture enhancements for a mesh based NoC architecture.