Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Algorithms and Tools for Network on Chip Based System Design
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A Power and Performance Model for Network-on-Chip Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
Power-aware communication optimization for networks-on-chips with voltage scalable links
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Packetized On-Chip Interconnect Communication Analysis for MPSoC
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
LiPaR: A light-weight parallel router for FPGA-based networks-on-chip
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Quality-of-service and error control techniques for mesh-based network-on-chip architectures
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
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Complex Systems-on-Chip (SoC) with multiple interconnected stand-alone designs require high scalability and bandwidth. Network-on-Chip (NoC) is a scalable communication infrastructure able to tackle the communication needs of these SoCs. In this paper, we consider the optimization of a generic NoC to improve area and performance of NoC based architectures for dedicated applications. The generic NoC can be tailored to an application by changing the number of routers, by configuring each router to specific traffic requirements, and by choosing the set of links between routers and cores. The optimization algorithm determines the appropriate NoC and routers configuration to support a set of applications considering the optimization of area, and performance. The final solution will consist of an heterogeneous NoC with improved quality. The approach has been tested under different operating conditions assuming implementations on an FPGA.