Co-synthesis of a configurable SoC platform based on a network on chip architecture
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Area and performance optimization of a generic network-on-chip architecture
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Evaluation of static and dynamic task mapping algorithms in NoC-based MPSoCs
SOC'09 Proceedings of the 11th international conference on System-on-chip
Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms
Journal of Systems Architecture: the EUROMICRO Journal
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Network on Chip (NoC) is a new paradigm for designing core based System on Chip. It supports high degree of reusability and is scalable. In this paper, an efficient Two-Step Genetic Algorithm and the correlated software will be described mapping concurrent applications, which are described by parameterized multi-task-graph, onto a NoC with two dimensional mesh of switches as a communication backbone and populated with a known set of IP cores as computational resources. The algorithm proposes mathematical delay models and finds a good method of mapping vertices of the multi-task-graph to available cores so that every single task graph can meet its respective deadline. The correlated software has two separate tools. One can freely generate any NoC backbone and multi-task-graph for test. The other achieves Two-Step Genetic Algorithm and can give the design result within one minute on a PC platform. It also provides facilities for viewing synthetic task graphs and the working progress of genetic algorithm.