CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A system-level synthesis algorithm with guaranteed solution quality
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Algorithms and Tools for Network on Chip Based System Design
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Power-Aware Communication Optimization for Networks-on-Chips with Voltage Scalable Links
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs
IEICE - Transactions on Information and Systems
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The constant increase of gate capacity and performance of configurable hardware chips made it possible to implement systems-on-chip (SoC) able to tackle the demanding requirements of many embedded systems. In this paper, we propose an approach to the design space exploration of a configurable SoC (CSoC) platform based on a network on chip (NoC) architecture for the execution of dataflow dominated embedded systems. The approach has been validated with the design of a color image compression algorithm in an FPGA.