25 years of the international symposia on Computer architecture (selected papers)
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Design of Cam-E-leon, a Run-Time Reconfigurable Web Camera
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
A Virtual Hardware Operating System for the Xilinx XC6200
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
A dynamic reconfiguration run-time system
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Online Scheduling and Placement of Real-time Tasks to Partially Reconfigurable Devices
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Proceedings of the 41st annual Design Automation Conference
Operating-system controlled network on chip
Proceedings of the 41st annual Design Automation Conference
Online Scheduling for Block-Partitioned Reconfigurable Devices
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks
IEEE Transactions on Computers
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Run-time support for heterogeneous multitasking on reconfigurable SoCs
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
LiPaR: A light-weight parallel router for FPGA-based networks-on-chip
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Virtual channels in networks on chip: implementation and evaluation on hermes NoC
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Placement of intermodule connections on partially reconfigurable devices
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
A Reconfiguration Manager for Dynamically Reconfigurable Hardware
IEEE Design & Test
Co-synthesis of a configurable SoC platform based on a network on chip architecture
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Networks on chips for high-end consumer-electronics TV system architectures
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Area and performance optimization of a generic network-on-chip architecture
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
A Simple Data Transfer Technique Using Local Address for Networks-on-Chips
IEEE Transactions on Parallel and Distributed Systems
Support for partial run-time reconfiguration of platform FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
Proceedings of the 44th annual Design Automation Conference
NoC design flow for TDMA and QoS management in a GALS context
EURASIP Journal on Embedded Systems
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Run-time integration of reconfigurable video processing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficiently scheduling runtime reconfigurations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Network of Time-Division Multiplexed Wiring for FPGAs
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
CuNoC: A dynamic scalable communication structure for dynamically reconfigurable FPGAs
Microprocessors & Microsystems
PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs
IEICE - Transactions on Information and Systems
A routing-table-based adaptive and minimal routing scheme on network-on-chip architectures
Computers and Electrical Engineering
Configuration Merging in Point-to-Point Networks for Module-Based FPGA Reconfiguration
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
On a web-graph-based micronetwork architecture for SoCs
International Journal of Computers and Applications
A task graph execution manager for reconfigurable multi-tasking systems
Microprocessors & Microsystems
Proceedings of the Conference on Design, Automation and Test in Europe
A configuration memory hierarchy for fast reconfiguration with reduced energy consumption overhead
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A distributed object system approach for dynamic reconfiguration
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
OveRSoC: a framework for the exploration of RTOS for RSoC platforms
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
GNLS: a hybrid on-chip communication architecture for SoC designs
International Journal of High Performance Systems Architecture
A reconfigurable computing platform for real time embedded applications
Microprocessors & Microsystems
A new metric for on-line scheduling and placement in reconfigurable computing systems
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part II
Reconfigure router design and evaluation for the FPGA-friendly SoCWire network-on-chip
Proceedings of the Annual FPGA Conference
Decentralized control for dynamically reconfigurable FPGA systems
Microprocessors & Microsystems
Energy and throughput aware fuzzy logic based reconfiguration for MPSoCs
Journal of Intelligent & Fuzzy Systems: Applications in Engineering and Technology
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Multimedia support appears on embedded platforms, such as WAP for mobile phones. However, true multimedia applications require both the computation power that only dedicated hardware can provide and the flexibility of software implementations. To this end, we are investigating reconfigurable architectures, composed of an instruction-set processor running software processes and coupled to an FPGA on which hardware tasks are spawned by dynamic partial reconfiguration. This paper focuses on two main aspects. It explains how separating communication from computation enables hardware multi-tasking and it describes our implementation of a fixed communication-layer that decouples the computation elements, allowing them to be dynamically reconfigured. This communication layer is an interconnection network, implemented on a Virtex FPGA, allowing fast synchronous communication between hardware tasks implemented on the same matrix. The network is a 2D torus and uses wormhole routing. It achieves transfer rates up to 77.6 MB/s between two adjacent routers, when clocked at 40 MHz. Interconnection networks on FPGAs allow fine-grain dynamic partial reconfiguration and make hardware multi-tasking a reality.