Dynamic reconfiguration of FPGAs
Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
On-chip communication architecture for OC-768 network processors
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Micro-Network for SoC: Implementation of a 32-Port SPIN network
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Packet Routing in Dynamically Changing Networks on Chip
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Dynamic Interconnection of Reconfigurable Modules on Reconfigurable Devices
IEEE Design & Test
A reconfigurable computing platform for real time embedded applications
Microprocessors & Microsystems
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The growing complexity of integrated circuits imposes to the designers to change and direct the traditional bus-based design concepts towards NoC-based. Networks on-chip (NoCs) are emerging as a viable solution to the existing interconnection architectures which are especially characterized by high level of parallelism, high performances and scalability. The already proposed NoC architectures in the literature are destined to System-on-chip (SoCs) designs. For a FPGA-based system, in order to take all benefits from this technology, the proposed NoCs are not suitable. In this paper, we present a new paradigm called CuNoC for intercommunication between modules dynamically placed on a chip for the FPGA-based reconfigurable devices. The CuNoC is based on a scalable communication unit characterized by unique architecture, arbitration policy base on the priority-to-the-right rule and modified XY adaptive routing algorithm. The CuNoC is namely adapted and suited to the FPGA-based reconfigurable devices but it can be also adapted with small modifications to all other systems which need an efficient communication medium. We present the basic concept of this communication approach, its main advantages and drawbacks with regards to the other main already proposed NoC approaches and we prove its feasibility on examples through the simulations. Performance evaluation and implementation results are also given.