Reconfigurable massively parallel computers
Reconfigurable massively parallel computers
PACT XPP—A Self-Reconfigurable Data Processing Architecture
The Journal of Supercomputing
Online Scheduling and Placement of Real-time Tasks to Partially Reconfigurable Devices
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Dynamic Reconfiguration: Architectures and Algorithms (Series in Computer Science (Kluwer Academic/Plenum Publishers).)
Design of adaptive multiprocessor on chip systems
Proceedings of the 20th annual conference on Integrated circuits and systems design
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
Allocation heuristics and defragmentation measures for reconfigurable systems management
Integration, the VLSI Journal
Run-time adaptive on-chip communication scheme
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
Dynamic power optimization by exploiting self-reconfiguration in Xilinx Spartan 3-based systems
Microprocessors & Microsystems
CuNoC: A dynamic scalable communication structure for dynamically reconfigurable FPGAs
Microprocessors & Microsystems
ROAdNoC: runtime observability for an adaptive network on chip architecture
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Reconfigurable Networks on Chip: DRNoC architecture
Journal of Systems Architecture: the EUROMICRO Journal
Flexible interconnection network for dynamically and partially reconfigurable architectures
International Journal of Reconfigurable Computing - Special issue on selected papers from spl 2009 programmable logic and applications
Priority-based packet communication on a bus-shaped structure for FPGA-systems
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
2D defragmentation heuristics for hardware multitasking on reconfigurable devices
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Interconnect estimation for mesh-based reconfigurable computing
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
A multi-level design methodology of multistage interconnection network for MPSOCs
International Journal of Computer Applications in Technology
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An important issue in reconfigurable computing is to provide communication between dynamically connected modules. This article describes routing algorithms for two architectures and analyzes the feasibility of these solutions for real-life applications.