Networks on Silicon: Blessing or Nightmare?
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
Designing an Operating System for a Heterogeneous Reconfigurable SoC
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Operating-system controlled network on chip
Proceedings of the 41st annual Design Automation Conference
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Dynamic Interconnection of Reconfigurable Modules on Reconfigurable Devices
IEEE Design & Test
A dynamically reconfigurable packet-switched network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
A Fast Emulation-Based NoC Prototyping Framework
RECONFIG '08 Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs
| Hi-index | 0.00 |
To cover the complexity of future systems, where thousands and hundreds of heterogeneous cores have to be interconnected, new on-chip communication solutions are being searched. In this context, Networks on Chip (NoCs) have been studied as bus alternative. However, the inclusion of NoCs' broad design space increases even more the complexity of design flows. Additionally, today electronic industry demands drastic time to market reduction and improved device diversity. On the other side, reconfigurable devices have had an impressive evolution and now, they are complex heterogeneous platforms which include a broad variety of embedded cores. Furthermore, today it is possible to embed reconfigurable arrays in application-specific integrated circuits and thus create highly flexible systems. These tendencies provide support to the idea of reconfigurable on-chip communication, which can reduce the system design time and permit to adapt their characteristics to currently running applications. This paper overviews some reconfigurable NoCs' state of the art solutions and describes a reconfigurable on-chip communication approach, called DRNoC, which explores the highest possible flexibility and is not limited to NoCs. An important aspect considered in this paper is real implementations and therefore, all the solutions discussed along it, including DRNoC, have been validated on FPGAs. The paper also highlights some technology restrictions of currently available FPGA reconfiguration techniques that do not permit to test real-live examples on such systems.